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5623420 Method and apparatus to distribute spare cells within a standard cell region of an integrated circuit  
A method and apparatus to distribute spare cells into a standard cell region of an integrated circuit is described. An initial layout of standard cells is first generated by a place and route tool....
5608245 Array on substrate with repair line crossing lines in the array  
A repair structure for an array with first and second sets of lines that cross includes a repair line extending within the array, approximately parallel to at least one line in the first set and...
5600569 Method, system, and apparatus for automatically designing logic circuit, and multiplier  
With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a...
5598347 Layout method for designing an integrated circuit device by using standard cells  
An integrated circuit device is provided, in which optimization design can be made for a short term to suppress power consumption of the integrated circuit device and improve the maximum operation...
5586319 Netlist editor allowing for direct, interactive low-level editing of netlists  
A custom netlist editor is provided in which low-level netlist editing procedures may be employed by a user to directly modify a netlist in its native format. The custom netlist editor eliminates...
5574655 Method of allocating logic using general function components  
A method is described for configuring a general symbol to represent a specific symbol indicated by a user. The specific symbols are part of a library. A general symbol for which optimized...
5561607 Method of manufacture of multi-cell integrated circuit architecture  
A standard cell topography has a generally rectangular topography, circumscribed by a set of four mutually orthogonal cell boundary edges. Coupled in circuit with a standard AND gate circuit within...
5561789 Power bus having power slits and holes embodied therein, and method for making the same  
An intersect area of an apparatus having a plurality of power buses, and a method for making the same. An intersect area is defined by an overlap region where a first and second power bus overlap....
5547740 Solderable contacts for flip chip integrated circuit devices  
A flip chip integrated circuit device (110) is provided having a surface, a perimeter, and solder bumps (112) located on the surface. At least one solder bump (112), and preferably a plurality of...
5544070 Programmed programmable device and method for programming antifuses of a programmable device  
A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current...
5537332 Stack macro order optimizing method  
An automated method for optimally ordering macros within a semiconductor chip data-path stack is disclosed. Each stack macro is assumed to have at least one predetermined bus connection with...
5530378 Cross point interconnect structure with reduced area  
An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based...
5526276 Select set-based technology mapping method and apparatus  
A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic...
5521833 Method for programming programmable integrated circuits  
Circuit-associated programming signals and at least one additional, circuit-associated programming routine are generated and are then arranged in a testing device. The function check of printed...
5519629 Tileable gate array cell for programmable logic devices and gate array having tiled gate array cells  
A logic and routing cell for constructing a programmable gate array. The gate array may be constructed by tiling a wafer surface with this single logic and routing cell design. The logic and...
5519627 Datapath synthesis method and apparatus utilizing a structured cell library  
A datapath circuit synthesizer converts an HDL circuit specification into a circuit netlist. The behavioral description of the specified circuit is divided into two distinct parts: datapath logic...
5519630 LSI automated design system  
Together with circuit data of circuit elements, there is stored, in a memory device, external specification information of each of the circuit elements, the information including (i) function...
5504755 Testable programmable logic array  
A testable PLA includes a PLA comprising an AND plane and an OR plane comprising input lines, output lines, and product term lines which are grouped into at least two groups; a selector circuit for...
5502648 Data processing method of generating integrated circuits using prime implicants  
An integrated circuit structure is generated to perform a given combinational function. A data processing system generates the integrated circuit structure when provided with an input specification...
5502645 Behavioral synthesis for reconfigurable datapath structures  
High level synthesis of datapaths has traditionally concentrated on synthesizing a specific implementation for a given computational problem. Methods to compose a reconfigurable BISR...
5499192 Method for generating logic modules from a high level block diagram  
A set of module generators produce optimized implementations of particular circuit logic arithmetic functions for Field Programmable Gate Arrays (FPGAs) or other digital circuits. The module...
5499191 Multi-level logic optimization in programmable logic devices  
During compiling, a PLD circuit design system inserts nodes in the two level sum-of-product representation of the target circuit at function and procedure boundaries, the carries between bits of...
5493506 Integrated circuit device and method of designing same  
A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an...
5490074 Constant delay interconnect for coupling configurable logic blocks  
A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing...
5477467 Shrinkable BiCMOS circuit layout  
A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the...
5477475 Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus  
A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is...
5475624 Test generation by environment emulation  
Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the...
5471397 Identifying subsets of noise violators and contributors in package wiring  
A method for identifying a minimal subset of noise violator nets that can be removed to ensure that no net has quiet noise that exceeds a specified maximum noise. Nets and the coupled noise between...
5463560 Semiconductor integrated circuit device  
The IC according to this invention has a semiconductor chip which includes a first and a second pad lines consisting of a plurality of pads connected respectively to the corresponding plurality of...
5461577 Comprehensive logic circuit layout system  
Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each...
5452227 Method and apparatus for converting a programmable logic device designed into a selectable target gate array design  
The present invention is a translation system that translates a definition of a prototyped programmable device defined in a programmable device specification into a generic behavioral model of the...
5452229 Programmable integrated-circuit switch  
A non-volatile, in-system programmable integrated-circuit switch has horizontal conductive lines and vertical conductive lines. A programmable interconnect cell including a floating gate transistor...
5452231 Hierarchically connected reconfigurable logic assembly  
A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are...
5452239 Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system  
An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation...
5448496 Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system  
A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are...
5438681 Topography for CMOS microcomputer  
The topography of an 84 lead CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. The chip includes...
5432719 Distributed memory architecture for a configurable logic array and method for using distribution memory  
This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired...
5422823 Programmable gate array device having cascaded means for function definition  
A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a...
5414637 Intra-module spare routing for high density electronic packages  
A method of fabricating a high density electronic package is disclosed. The package includes a module of laminated semiconductor chips, including spare chip(s) and a supporting substrate with a...
5414638 Programmable interconnect architecture  
A programmable interconnect system includes a two-level hierarchal structure of programmable interconnect chips on a circuit board. The first-level, or "local", interconnect chips are connected to...
5400262 Universal interconnect matrix array  
A universal interconnect matrix area array or crosspoint switch is comprised of a first set of conductive leads formed in a first direction, a second set of conductive leads formed in a second...
5394030 Programmable logic device  
A programmable logic device includes groups of AND logic function gates, the AND logic function gates in each group coupled to a logic OR function output gate associated with that AND logic...
5394338 Module cell generating device for a semiconductor integrated circuit  
A module cell generating device of a semiconductor integrated circuit includes a parameter input part for applying a designation parameter, a basic cell group storing the basic cells, and a basic...
5384710 Circuit level netlist generation  
A design layout sequence for an application specific integrated circuit such as a gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing...
5377123 Programmable logic device  
A programmable logic device includes means for operating a computing element to compile a set of state-machine states in an incompletely specified state-machine. The state-machine states are...
5369595 Method of combining gate array and standard cell circuits on a common semiconductor chip  
A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with...
5359536 Programmable gate array with improved interconnect structure, input/output structure and configurable logic block  
A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a...
5348902 Method of designing cells applicable to different design automation systems  
In a method of designing cells applicable to different first and second design automation systems, first and second cells circuit-designed by the first and second design automation systems,...
5337255 Method for implementing set/reset synchronously or asynchronously in a programmable logic device  
A method is disclosed for allowing a user to enter a register symbol in a schematic diagram and attach to the register symbol both asynchronous and synchronous reset inputs. The method further...
5311079 Low power, high performance PLA  
A programmable logic array (PLA) is provided with a decoder at the input. Each product term line of the PLA has an associated power switch that is controlled by an output of the decoder. Only a...
Matches 701 - 750 out of 800 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >