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6353920 Method for implementing wide gates and tristate buffers using FPGA carry logic  
A method for implementing wide gates and tristate buses using FPGA carry logic. Wide gate logic functions and tristate buses are detected and implemented with a plurality of LUTs and carry...
6353921 Hardwire logic device emulating any of two or more FPGAs  
A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so...
6349346 Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit  
A reconfigurable system is arranged to have separate control and the data paths. The control path is set up using control fabric units which use an associated state machine to produce an address to...
6339835 Pseudo-anding in dynamic logic circuits  
A typical domino logic circuit has a foot device, which is the n-type evaluate transistor coupled between the n-type logic circuitry receiving the data inputs and the ground potential. This AND...
6336208 Delay optimized mapping for programmable gate arrays with multiple sized lookup tables  
A process for mapping logic nodes to a plurality of sizes of lookup tables in a programmable gate array. A node and its predecessor nodes are selectively collapsed into a first single node as a...
6336209 Information processing system that processes portions of an application program using programmable logic circuits  
By reusing circuit information designed in the past, the amount of computation for combining circuit information for layout and wirings is significantly reduced. A memory part stores a plurality of...
6334208 Method and apparatus for in-system programming with a status bit  
Apparatus and method for programming a programmable logic device (PLD) using a status bit to indicate whether in-system programming (ISP) has been completed. Complex electronic systems often use...
6334207 Method for designing application specific integrated circuits  
An ASIC design methodology in which portions of the ASIC are implemented in silicon or other suitable semiconductor technology at an early stage in the design flow through the use of a series of...
6324677 Integrated circuit layout design  
A circuitry layout design allows more functional circuitry to be placed on an integrated circuit by placing functional circuitry on the unused silicon layer of the power I/O strip, which is located...
6321371 Insertion of spare logic gates into the unused spaces between individual gates in standard cell artwork  
Apparatus for placing and routing an integrated circuit, the apparatus comprising one or more computer readable storage media. Computer readable program code is stored in the one or more computer...
6314551 System processing unit extended with programmable logic for plurality of functions  
An integrated circuit including a main system processing unit which can be extended using a plurality of programmable logic unit for a plurality of possible functions, and a system for programming...
6314550 Cascaded programming with multiple-purpose pins  
A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of...
6308312 System and method for controlling leakage current in an integrated circuit using current limiting devices  
A circuit 10 is provided that comprises a source resistance transistor 12 connected to a common node 14. A word line driver circuit 18 receives current if it is the word line driver selected from...
6304997 Method and circuit arrangement for multiplying frequency  
A method and circuit arrangement for frequency multiplication. A plurality of circuit modules for realizing Chebyshev polynomials of the nth order T n (x)) are provided. The Chebyshev polynomials...
6304999 Method and apparatus for embedded process control framework in tool systems  
The present invention provides for a method and an apparatus for implementing an embedded process control into a manufacturing tool system. At least one semiconductor device is processed. An...
6301695 Methods to securely configure an FPGA using macro markers  
A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a...
6301696 Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template  
A method of making an integrated circuit (IC) includes establishing an initial design for a field-programmable gate array (FPGA) to be included in the IC that includes programmable connections that...
6298319 Incremental compilation of electronic design for work group  
A work group computing system for facilitating programmable logic device design among multiple engineers has a global work space including design project source files, a compilation basis, a...
6292925 Context-sensitive self implementing modules  
The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for...
6289496 Placement of input-output design objects into a programmable gate array supporting multiple voltage standards  
A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites...
6289497 Method and apparatus for N-NARY hardware description language  
A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming...
6289412 Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification  
A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for...
6279145 Apparatus and method for isolating noisy signals in an integrated circuit  
A circuit to reduce erroneous signal glitches in the presence of overshoot and undershoot signals includes an output node and an input node to alternately receive overshoot and undershoot signals....
6272669 Method for configuring a programmable semiconductor device  
A method is provided for configuring a programmable semiconductor device. The method includes using the configuration data of a macro (53A) or a plurality of macros to configure the programmable...
6272670 Distributed charge source  
In one embodiment, a plurality of atomic charge pumps (52, 54, 56) are connected together in series to form a distributed charge source (24). The atomic charge pumps (52, 54, 56) are operated...
6263482 Programmable logic device having macrocells with selectable product-term inversion  
A programmable logic device is provided that contains macrocells with selectable inversion circuitry. The macrocells may be organized in groups of macrocells called logic array blocks. The logic...
6256604 Memory integrated with logic on a semiconductor chip and method of designing the same  
In a structure and a designing method of a memory integrated with a logic, a memory macro comprises L memory array blocks 1-1, 1-2, . . . 1-L each including memory cell arrays each with a storage...
6243851 Heterogeneous method for determining module placement in FPGAs  
The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for...
6237129 Method for constraining circuit element positions in structured layouts  
The invention supplies a method whereby placement information for elements of a logic module is specified in such a manner that specific coordinates need not be included. This method can be applied...
6233723 Circuit behavioral information analysis apparatus and a method of analyzing behavioral information of a circuit  
The present invention provides stimuli generators, methods of analyzing a cell, methods of generating at least one stimuli, and methods of characterizing delay of a cell. One method of analyzing a...
6230307 System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects  
A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement...
6230308 Method of assembling modules to form a complex integrated circuit and corresponding module architecture  
The method relates to assembling modules for an integrated circuit comprising at least a plurality of modules. The method provides for the formation of at least one module architecture which...
6223146 Method and apparatus for manufacturing a programmed electronic control unit for use in an anti-lock braking (ABS) system  
Method and apparatus are provided in a manufacturing area wherein a semiconductor having nonvolatile memory space is automatically programmed, tested, marked and mounted at a predetermined position...
6219824 Integrated circuit having a programmable input/output processor that is used for increasing the flexibility of communications  
A system and method for increasing the flexibility of communications being performed by an integrated circuit Specifically, an integrated circuit including a programmable input/output processor and...
6216257 FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks  
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable...
6216259 Configuration of programmable logic devices with routing core generators  
A system and method for configuration of a programmable logic device using routing cores. A program executing on a processor includes instructions that select functions to be provided by the...
6216258 FPGA modules parameterized by expressions  
The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for...
6212670 Method for implementing a programmable logic device having look-up table and product-term circuitry  
A programmable monolithic integrated logic circuit that includes look up table circuits and programmable logic array-like circuits. The integrated circuit can include a first number of the look up...
6212625 General purpose dynamically programmable state engine for executing finite state machines  
A general purpose dynamically programmable state engine dynamically executes finite state machines and finite state machine models. The state engine includes an input and filter unit, a storage...
6202198 Programmable integrated analog input/output circuit with distributed matching memory array  
A program controlled integrated circuit having an input path for receiving an analog signal with given attributes and using a program controlled sequence of treatment stages to generate a...
6202197 Programmable digital signal processor integrated circuit device and method for designing custom circuits from same  
An apparatus architecture is provided which permits an easily programmed apparatus (10) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The...
6185725 Apparatus and method for partitioning logic into a programmable logic device  
A method of partitioning logic into a programmable logic device includes the steps of synthesizing a logic design into a network of hierarchical components. Each hierarchical component is then...
6178541 PLD/ASIC hybrid integrated circuit  
An integrated circuit comprised of a customized circuit portion and a programmable logic portion that is interfaced to the customized circuit. The custom circuit and the programmable circuit are...
6175951 Method for fabricating a customer-configured integrated circuit and customer-configured integrated circuit for exclusive use by a customer background of the invention  
An integrated circuit has an integrated circuit core formed with an application core circuit portion, a code generating circuit portion for generating a customer-specific code assigned to the...
6173245 Programmable logic array device design using parameterized logic modules  
The design of logic for implementation in programmable logic array integrated circuit devices is facilitated by allowing various characteristics of modules in the logic design to be parameterized....
6173434 Dynamically-configurable digital processor using method for relocating logic array modules  
A method for relocating modules within a programmable logic array is disclosed and used to produce a dynamically-reconfigurable digital processor. The method consists of creating relocatable...
6167560 One-cold encoding method for low power operation in a complex programmable logic device  
A method for selecting the state assignments of a complex programmable logic device (CPLD) to minimize power consumption. Within the CPLD, a plurality of macrocells are selected to store a...
6163167 Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area  
A method for generating a two-turn programmable routing structure is provided for a programmable logic device that provides a high degree of routing flexibility, with lane-changing capability,...
6154873 Layout designing method and layout designing apparatus  
A hierarchical layout designing method for an LSI has the step of determining the layout positions and shapes of hard macro blocks and a soft macro block, the step of forming a wiring which...
6134704 Integrated circuit macro apparatus  
An apparatus comprising a base macro, with fixed timing, surrounded by, and connected to, at least one selectable feature macro. The features of the apparatus may be selectively provided by...
Matches 601 - 650 out of 801 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >