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6510546 Method and apparatus for pre-routing dynamic run-time reconfigurable logic cores  
A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration...
6507942 Methods and circuits for testing a circuit fabrication process for device uniformity  
Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is...
6505341 System and method for programming a logic control unit  
A system and process for generating a control program for execution by a programmable logic control unit including the steps of: providing a variable editing user interface allowing a user to...
6505337 Method for implementing large multiplexers with FPGA lookup tables  
A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA...
6496972 Method and system for circuit design top level and block optimization  
In a computer-implemented synthesis system, a method of optimizing a design of an integrated circuit device. The optimization process includes the computer-implemented steps of accessing a circuit...
6496965 Automated design of parallel drive standard cells  
Methods and apparatuses for automated design of parallel drive standard cells are disclosed. The capacitive load to be driven by a particular output of a standard cell is determined. The driving...
6493648 Method and apparatus for logic synthesis (inferring complex components)  
An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a...
6490712 Method and system for identifying configuration circuit addresses in a schematic hierarchy  
A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a...
6490715 Cell library database and design aiding system  
A cell library database includes function information of standard cells which are basic circuits forming a logical device, each of the standard cell comprising at least one of power supply terminal...
6490716 Automated design of processor instruction units  
An automated method for designing a processor's control path employs program routines that synthesize the control path based on the processor's instruction format and data path specification. It...
6490714 Apparatus and method for in-system programming of a field programmable logic device using device-specific characterization data  
A programmable logic device includes field programmable logic circuits and an internal programming circuit. The internal programming circuit includes a memory to store characterization data...
6484304 Method of generating application specific integrated circuits using a programmable hardware architecture  
A method for generating an application specific integrated circuit including providing a software configurable semiconductor integrated circuit having a fixed hardware architecture that includes a...
6480817 Integrated circuit I/O pad cell modeling  
A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad...
6480815 Path dependent power modeling  
A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic...
6481001 Method and system for proactively debugging fitting problems in programmable logic devices  
A method and system for automatically proactively debugging fitting problems in programmable devices. Automatic fitters are computer programs that place and route circuit resources within a...
6477696 Routing definition to optimize layout design of standard cells  
A novel routing rule definition for standard cells placement is disclosed. The method comprises following steps. At beginning, a statistical analysis is carried out to analyze the frequency of...
6477695 Methods for designing standard cell transistor structures  
Disclosed are methods for designing standard cell transistor layouts for minimizing transistor delays and for minimizing power consumption. The method of minimizing transistor delays includes...
6473884 Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis  
A method and system for equivalence checking of logical circuits using iterative circuit reduction and satisfiability techniques provide improved performance in computer-based verification and...
6467075 Resolution of dynamic memory allocation/deallocation and pointers  
One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemented in hardware or...
6467073 Method and apparatus for the automated generation of single and multistage programmable interconnect matrices with automatic routing tools  
A method to automatically generate a single and/or multistage PIM, comprising the steps of (A) generating a schematic that matches a layout of the PIM, (B) optionally generating a first stage and a...
6467074 Integrated circuit architecture with standard blocks  
An integrated circuit (IC) architecture with STANDARD BLOCKs. The IC architecture forms a layout that includes a plurality of STANDARD BLOCKs, top-level cells, and hard IP blocks. The STANDARD...
6467070 Design support apparatus for semiconductor devices  
A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it....
6467072 Method of placement and routing for an array device  
The invention provides a method of placement and routing for an array device in an integrated circuit (IC). In the method, a schematic script file used to describe placement for the array device is...
6463576 Method for designing an ASIC and ASIC designing apparatus  
A method for designing an ASIC has a first step of generating circuit data that includes a large-scale hardware macro made up of primitive macros; a second step of extracting, from the circuit data...
6463565 Method for designing object-oriented table driven state machines  
A finite state machine is implemented by encapsulating the portions of a state table, which are associated with each state in a state object. Each state object is instantiated when the associated...
6460172 Microprocessor based mixed signal field programmable integrated device and prototyping methodology  
A user-programmable integrated circuit that includes over the same silicon die a) a set of programmable logic cells such as the ones used in already reported FPGAs; b) a set of programmable mixed...
6457167 Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program  
Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O...
6453456 System and method for interactive implementation and testing of logic cores on a programmable logic device  
A system and method for developing a circuit design for a programmable logic device. A tool is provided for interactively modifying a configuration bitstream, downloading the bitstream to a...
6453451 Generating standard delay format files with conditional path delay for designing integrated circuits  
A method of generating a back-annotated standard delay format file for designing integrated circuits with conditional/moded delays is disclosed that includes the steps of receiving as inputs a main...
6449576 Network processor probing and port mirroring  
A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of...
6446242 Method and apparatus for storing a validation number in a field-programmable gate array  
An apparatus including a field-programmable gate array (FPGA) where the FPGA includes a plurality of X signal lines, a plurality of Y signal lines, and a plurality of memory cells. A first set of...
6446248 Spare cells placement methodology  
Methods for designing an integrated circuit is disclosed. In the present invention, the integrated circuit is first created by placing and routing standard cells of the integrated circuit. After...
6446250 Input/output cell generator  
An automated method for generating input/output (I/O) cells for an integrated circuit chip is provided. The method includes receiving a width parameter (as user requested data) for a desired I/O...
6434736 Location based timing scheme in memory design  
A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense...
6430736 Method and apparatus for evolving configuration bitstreams  
A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets...
6425115 Area efficient delay circuits  
The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell...
6425116 Automated design of digital signal processing integrated circuit  
An apparatus, program product and method are provided for use in automating the design of a custom DSP integrated circuit from a preexisting DSP core block and one or more additional circuit blocks...
6421817 System and method of computation in a programmable logic device using virtual instructions  
An FPGA configuration provides a virtual instruction. In a generic computation, the output pattern of a first instruction is compared to the input pattern of a second instruction. If the input and...
6415429 Field programmable analogue processor  
A programmable analogue device including an array of cells. Each cell is controllable for performing a predetermined set of analogue functions. The cells are selectively interconnected for...
6408428 Automated design of processor systems using feedback from internal measurements of candidate systems  
An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor...
6408422 Method for remapping logic modules to resources of a programmable gate array  
A method is provided for remapping logic modules to resources of a programmable gate array. Connections are specified between at least two logic modules, wherein each module has a respective...
6405356 Method of automatic placement for an arrayed-element device  
A method of automatic placement for an arrayed-element device, which automatically generates a schematic script for the arrayed-element device based on topological specifications, a netlist, and...
6385761 Flexible width cell layout architecture  
The semiconductor cell library of the present invention includes a plurality of semiconductor cell definitions. At least one of the semiconductor cell definitions includes a base cell and at least...
6381733 System and method for instantiating logic blocks within an FPGA  
A copying logic block for, and a method of, programming an FPGA and a modular music synthesis processor incorporating the copying logic block or the method. In one embodiment, the copying logic...
6374203 Method of modeling circuit cells with distributed serial loads  
A plurality of serially coupled circuit cells ( 12-20 ) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is...
6367063 Method and apparatus for selectively performing a plurality of logic operations and memory functions  
A logic device for performing a plurality of logic functions employs a plurality of logic elements interconnected by a plurality of switching boxes. A set of configuration bits are provided to the...
6367061 Semiconductor integrated circuit and manufacturing method therefor, semiconductor macro cell and automatic layout method therefor, and mask processing method  
In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is...
6367059 Carry chain standard cell with charge sharing reduction architecture  
A standard cell circuit architecture and design is provided by way of this disclosure. The standard cell has a plurality of sub-cells that are designed to function together to generate a result and...
6357037 Methods to securely configure an FPGA to accept selected macros  
A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from...
6353332 Methods for implementing CAM functions using dual-port RAM  
A method for implementing a CAM function using a dual-port RAM. Data is stored in the memory array of the dual-port RAM as decoded “one hot” data words such that each data word is stored in one...
Matches 551 - 600 out of 801 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >