|
Match
|
Document |
Document Title |
|
|
7631283 |
Methods and apparatus for defining manhattan power grid structures having a reduced number of vias
A method for producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage...
|
|
|
7624367 |
Method and system for routing
Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to...
|
|
|
7620923 |
Run-time efficient methods for routing large multi-fanout nets
A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a...
|
|
|
7614027 |
Methods for forming a MRAM with non-orthogonal wiring
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be...
|
|
|
7603644 |
Integrated circuit routing and compaction
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel,...
|
|
|
7603642 |
Placer with wires for RF and analog design
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads...
|
|
|
7603599 |
Method to test routed networks
Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources...
|
|
|
7600209 |
Generating constraint preserving testcases in the presence of dead-end constraints
Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is...
|
|
|
7596774 |
Hard macro with configurable side input/output terminals, for a subsystem
A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time...
|
|
|
7594215 |
Method and system for optimized automated IC package pin routing
An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is...
|
|
|
7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by...
|
|
|
7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid
A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference...
|
|
|
7587696 |
Semiconductor device, layout method and apparatus and program
A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is...
|
|
|
7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
|
|
|
7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
|
|
|
7577933 |
Timing driven pin assignment
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design...
|
|
|
7576569 |
Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit
A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life...
|
|
|
7574686 |
Method and system for implementing deterministic multi-processing
Disclosed is a method, system, and computer program product for implementing a costed-search approach that supports concurrent operation on a multi-CPU system that enables out-of-order search...
|
|
|
7571412 |
Method and system for semiconductor device characterization pattern generation and analysis
A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device...
|
|
|
7571409 |
Circuit design device and circuit design program
A placement and routing processing unit performs placement and routing processing on a customer circuit based on design data. An embedded circuit generation processing unit refers to a library...
|
|
|
7568178 |
System simulation and graphical data flow programming in a common environment using wire data flow
Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various...
|
|
|
7568177 |
System and method for power gating of an integrated circuit
Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is...
|
|
|
7562330 |
Budgeting global constraints on local constraints in an autorouter
Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a...
|
|
|
7562329 |
Master-slice-type semiconductor integrated circuit having a bulk layer and a plurality of wiring layers and a design method therefor
In a master-slice-type semiconductor integrated circuit having a bulk layer on which a plurality of bulk patterns to realize specific circuit functions are formed, and a plurality of wiring layers...
|
|
|
7546569 |
Automatic trace determination method
An automatic trace determination process comprises the steps of: determining whether an inspection line connecting between two points that are to be a starting point and an end point intersects...
|
|
|
7543252 |
Migration of integrated circuit layout for alternating phase shift masks
Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to...
|
|
|
7543251 |
Method and apparatus replacing sub-networks within an IC design
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
|
|
|
7539893 |
Systems and methods for speed binning of integrated circuits
Methods and apparatus sort integrated circuits by maximum operating speed (f max ). The timing for a first set of critical timing paths is statistically characterized. The first set can be, for...
|
|
|
7536667 |
Method of semiconductor device and design supporting system of semiconductor device
A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval...
|
|
|
7536666 |
Integrated circuit and method of routing a clock signal in an integrated circuit
The various embodiments of the present invention relate to coupling clock signals between a plurality of data transceivers. According to one embodiment, a clock routing circuit having data...
|
|
|
7536665 |
User-guided autorouting
A mechanism is provided for the user to define a circuit design intent or strategy in the form of data that is stored with the design database. An autorouter then uses this guidance from the user...
|
|
|
7533361 |
System and process for manufacturing custom electronics by combining traditional electronics with printable electronics
A system and process for manufacturing custom printed circuit boards on pre-provided substrates, wherein the substrate is pre-provided with standard integrated circuits. The standard integrated...
|
|
|
7533358 |
Integrated sizing, layout, and extractor tool for circuit design
Method and system are disclosed for designing a circuit using an integrated sizing, layout, and extractor tool. In one embodiment, a method for designing a circuit including initializing a set of...
|
|
|
7530042 |
System and method for auto-routing jog elimination
A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width...
|
|
|
7523424 |
Method and system for representing analog connectivity in hardware description language designs
System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have...
|
|
|
7516433 |
Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long...
|
|
|
7512921 |
Method and apparatus for designing integrated circuit enabling the yield of integrated circuit to be improved by considering random errors
A layout method in a layout apparatus for layout of an integrated circuit includes placing a plurality of cells at approximate positions according to the circuit data and placing the plurality of...
|
|
|
7509616 |
Integrated circuit layout design system, and method thereof, and program
There is provided an integrated circuit layout design method capable of performing LVS verification in an early stage of layout design. Placement and routing means provides wiring and outputs a...
|
|
|
7509615 |
Circuit layout structure and method
A symmetrical circuit layout structure includes a number of signal wires, a ground wire and a dielectric layer. The signal wires include a first portion placed on a first plane and a second portion...
|
|
|
7506289 |
Approach for routing an integrated circuit
A computer-implemented approach for routing an integrated circuit using non-orthogonal routing is accomplished during two phases: a global routing phase and a detailed routing phase. During global...
|
|
|
7503026 |
Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor...
|
|
|
7500212 |
Method, apparatus and program for automatically routing semiconductor integrated circuit
Disclosed is an apparatus for performing automatic routing of a semiconductor integrated circuit, including an automatic routing and search processing unit for outputting post-routing layout data...
|
|
|
7500210 |
Chip area optimization for multithreaded designs
A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to...
|
|
|
7496878 |
Automatic wiring method and apparatus for semiconductor package and automatic identifying method and apparatus for semiconductor package
A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad...
|
|
|
7496874 |
Semiconductor yield estimation
A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant...
|
|
|
7490309 |
Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysis
A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the...
|
|
|
7487488 |
Predictable repeater routing in an integrated circuit design
A mechanism is disclosed for assigning repeaters to signal paths in an integrated circuit design. The mechanism involves reserving, in a first metal layer of the integrated circuit design, metal...
|
|
|
7480888 |
Design structure for facilitating engineering changes in integrated circuits
A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations...
|
|
|
7480887 |
Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring
A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure...
|
|
|
7480885 |
Method and apparatus for routing with independent goals on different layers
Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a...
|