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8185851 |
Memory building blocks and memory design using automatic design tools
The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example,...
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8185865 |
Methods for gate-length biasing using annotation data
Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or...
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8181128 |
Method and apparatus for determining a photolithography process model which models the influence of topography variations
One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a...
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8181145 |
Method and apparatus for generating a floorplan using a reduced netlist
One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist...
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8181149 |
Interface for managing multiple implementations of a functional block of a circuit design
Approaches for assembling an electronic circuit design. A processor performs operations including instantiating and coupling a plurality of instances of functional blocks in the design, including...
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8181148 |
Method for identifying and implementing flexible logic block logic for easy engineering changes
A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).
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8176447 |
Formation of masks/reticles having dummy features
A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method...
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8176463 |
Modeling and simulating device mismatch for designing integrated circuits
A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by...
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8176446 |
Method for compensating for variations in structures of an integrated circuit
A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b)...
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8156459 |
Detecting differences between high level block diagram models
A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive...
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8151222 |
Method for decomposing designed pattern layout and method for fabricating exposure mask using the same
A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality...
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8151236 |
Steiner tree based approach for polygon fracturing
Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points...
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8146050 |
Graphical program with physical simulation and data flow portions
Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various...
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8146032 |
Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs
One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die...
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8146048 |
System and method for removing T-point elements with unused stubs from a PCB layout design
A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or more T-point elements in the PCB...
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8141028 |
Structure for identifying and implementing flexible logic block logic for easy engineering changes
A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a...
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8141019 |
Method for optimizing of pipeline structure placement
A circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. The process employs a method for...
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8141026 |
Method and system for rapidly identifying silicon manufacturing defects
The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first...
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8132322 |
Automatic inserting method, system and device for PCB board
The present invention relates to the electronic manufacturing field and provides an automatic inserting method, an inserting system and an inserting device for a PCB board The method includes:...
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8136084 |
Arranging through silicon vias in IC layout
A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the...
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8135484 |
Work instruction sheet preparing device, method and program
A property of connection relationship information for identifying an internal/external connection of each point is registered in a part DB 1. When the part is one basic part representing a standard...
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8136072 |
Standard cell placement
A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit...
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8132137 |
Prediction of dynamic current waveform and spectrum in a semiconductor device
A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption...
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8132133 |
Automated isolation of logic and macro blocks in chip design testing
A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated...
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8127266 |
Gate-length biasing for digital circuit optimization
Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a...
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8127261 |
System for quickly specifying formal verification environments
Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module,...
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8122393 |
Integrated circuit transformer devices for on-chip millimeter-wave applications
Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer...
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8117585 |
System and method for testing size of vias
A system and method for testing size of vias reads a component group from a storage system and reads a via size of each via in the component group. If the via size of a via accords with a standard...
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8117586 |
Printed circuit board layout system and method thereof
A method for automatically checking signal areas includes: recording etching line information of etching lines which divide an internal plane of an opened PCB file into a plurality of signal areas,...
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8112737 |
Contact resistance and capacitance for semiconductor devices
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a...
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8112733 |
Method and apparatus for routing with independent goals on different layers
Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a...
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8112732 |
System and computer program product for diffusion based cell placement migration
A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells...
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8108823 |
User selected grid for logically representing an electronic circuit
A computer implemented method employs software on a system for generating a logical representation of an electronic circuit undergoing a design. A predetermined grid for the circuit being designed...
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8108824 |
Pattern verification method, method of manufacturing semiconductor device, and recording media
A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions,...
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8108822 |
Methodology for placement based on circuit function and latchup sensitivity
A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element...
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8099707 |
Field configured electronic circuits and methods of making the same
Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing...
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8099701 |
Efficient chip routing method and apparatus for integrated circuit blocks with multiple connections
Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout...
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8099708 |
I/O planning with lock and insertion features
A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon...
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8099706 |
Software product for semiconductor device design
A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a...
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8095896 |
Method and system of displaying an exposure condition
There is provided a device which may easily and visually judge which chip in an FEM wafer has a normal exposure condition, or which chip has an abnormal exposure condition. A feature quantity for a...
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8095905 |
Power supply wiring structure
Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and...
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8095898 |
Method and system for implementing electronic design entry
Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization...
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8091059 |
Method for diffusion based cell placement migration
A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces...
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8091055 |
Method and apparatus for managing violations and error classifications during physical verification
Some embodiments provide a system for managing violations during physical verification. The system may identify a design-rule-check (DRC) violation by applying a set of DRC rules to a layout. The...
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8091063 |
Method and apparatus for characterizing an integrated circuit manufacturing process
A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor...
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8086989 |
Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks
A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure...
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8086990 |
Method of correlating silicon stress to device instance parameters for circuit simulation
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard,...
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8082537 |
Method and apparatus for implementing spatially programmable through die vias in an integrated circuit
Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout...
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8078980 |
User defined wire appearance indicating communication functionality in a graphical programming environment
System and method for configuring a wire appearance in a graphical programming environment. A first data type (or class), or communication functionality between nodes, e.g., timing, or data...
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8079013 |
Hardware description interface for a high-level modeling system
A computer-implemented method of specifying a circuit design within a high-level modeling system (HLMS) can include, responsive to a scripted user input, instantiating a first and a second block...
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