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7620923 |
Run-time efficient methods for routing large multi-fanout nets
A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a...
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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617463 |
Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit
In a power supply port decision step, first, a required minimum number of power supply ports for use in a test is found based on power consumption information and the required minimum number of...
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7614028 |
Representation, configuration, and reconfiguration of routing method and system
Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of...
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7614027 |
Methods for forming a MRAM with non-orthogonal wiring
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be...
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7614025 |
Method of placement for iterative implementation flows
A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty...
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7607118 |
Techniques for using edge masks to perform timing analysis
Techniques are provided for more efficient timing analysis of user designs for programmable ICs. Initially, a graph is created that represents nodes and edges in a user design. Each edge in the...
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7607113 |
Wiring pattern determination method and computer program product thereof
A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions...
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7603644 |
Integrated circuit routing and compaction
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel,...
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7603642 |
Placer with wires for RF and analog design
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads...
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7603634 |
Various methods and apparatuses to preserve a logic state for a volatile latch circuit
An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state...
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7603599 |
Method to test routed networks
Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources...
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7595655 |
Retrieving data from a configurable IC
Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between...
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7594215 |
Method and system for optimized automated IC package pin routing
An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is...
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7594214 |
Maximum flow analysis for electronic circuit design
Disclosed are improved methods and mechanisms for congestion and maximum flow analysis for routing an integrated circuit design. In one approach, maximum flow analysis is performed by tessellating...
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7594207 |
Computationally efficient design rule checking for circuit interconnect routing design
Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements...
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7594206 |
Fault detecting method and layout method for semiconductor integrated circuit
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor...
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7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by...
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7590960 |
Placing partitioned circuit designs within iterative implementation flows
A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding...
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7587699 |
Automated system for designing and developing field programmable gate arrays
An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is...
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7587693 |
Apparatus and method of delay calculation for structured ASIC
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a...
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7584448 |
Constructing a model of a programmable logic device
A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of...
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7584447 |
PLD architecture for flexible placement of IP function blocks
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
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7581201 |
System and method for sign-off timing closure of a VLSI chip
A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in...
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7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
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7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
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7581197 |
Relative positioning of circuit elements in circuit design
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
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7580824 |
Apparatus and methods for modeling power characteristics of electronic circuitry
Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating...
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7577932 |
Gate modeling for semiconductor fabrication process effects
In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic...
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7574686 |
Method and system for implementing deterministic multi-processing
Disclosed is a method, system, and computer program product for implementing a costed-search approach that supports concurrent operation on a multi-CPU system that enables out-of-order search...
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7571418 |
Simulation site placement for lithographic process models
A method and system for performing the method are provided for designing a mask layout that includes selecting simulation sites for optical proximity correction (OPC) or mask verification, prior to...
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7571415 |
Layout of power device
A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The...
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7571412 |
Method and system for semiconductor device characterization pattern generation and analysis
A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device...
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7571411 |
Methods and apparatus for providing flexible timing-driven routing trees
A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source...
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7571410 |
Resonant tree driven clock distribution grid
An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein....
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7571409 |
Circuit design device and circuit design program
A placement and routing processing unit performs placement and routing processing on a customer circuit based on design data. An embedded circuit generation processing unit refers to a library...
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7565638 |
Density-based layer filler for integrated circuit design
A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may...
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7562330 |
Budgeting global constraints on local constraints in an autorouter
Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a...
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7562329 |
Master-slice-type semiconductor integrated circuit having a bulk layer and a plurality of wiring layers and a design method therefor
In a master-slice-type semiconductor integrated circuit having a bulk layer on which a plurality of bulk patterns to realize specific circuit functions are formed, and a plurality of wiring layers...
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7561534 |
Methods of network routing having improved resistance to faults affecting groups of links subject to common risks
A number of techniques are described for routing methods that improve resistance to faults affecting groups of links subject to common risks. One of these techniques accounts for failure potentials...
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7559044 |
Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit
An automatic design method of a semiconductor integrated circuit includes: increasing an interval between a plurality of wiring patterns provided on a chip region to relieve a density of the wiring...
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7559042 |
Layout evaluating apparatus
To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual...
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7559040 |
Optimization of combinational logic synthesis through clock latency scheduling
In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in...
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7555740 |
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis
Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an...
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7546569 |
Automatic trace determination method
An automatic trace determination process comprises the steps of: determining whether an inspection line connecting between two points that are to be a starting point and an end point intersects...
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7543251 |
Method and apparatus replacing sub-networks within an IC design
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
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7543249 |
Embedded switchable power ring
An integrated circuit comprises an embedded switchable power ring for supplying power to circuit modules ( 15.1, . . . , 15.5 ) arranged within the switchable power ring ( 13 ). The switchable...
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7539961 |
Library-based solver for modeling an integrated circuit
A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for...
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7539957 |
Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks
Methods and apparatus for testing integrated circuits are provided. Integrated circuits sometimes contain repeating blocks of identical circuitry. Each identical circuit block contains scan chain...
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7539184 |
Reconfigurable interconnect/switch for selectably coupling network devices, media, and switch fabric
A reconfigurable interconnect/switch for selectably coupling network devices, media, and switch fabric. The reconfigurable interconnect/switch enables network devices, such as network processor...
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