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7461361 Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method  
There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch...
7461359 Method and mechanism for determining shape connectivity  
A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of...
7458051 ECO cell for reducing leakage power  
A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line...
7454736 Automatic trace determination apparatus and computer program thereof  
An automatic trace determination apparatus comprises: first means that performs a first process sequentially for all intersections formed between tentative traces connecting between pads and...
7454720 Method for optimizing a layout of supply lines  
A method for optimizing a circuit layout is provided which optimizes a circuit layout as a result of utilizing unused tracks of the circuit layout to expand supply lines. In a first step, a circuit...
7454543 Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus  
In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus...
7451430 Apparatus and method for generating transistor model  
In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion...
7451424 Determining programmable connections through a switchbox of a programmable logic device  
A processor-implemented method is provided for determining programmable connections through a switchbox module of a programmable logic device (PLD) design. A netlist that describes the PLD design...
7451423 Determining indices of configuration memory cell modules of a programmable logic device  
A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A...
7451421 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies  
A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions,...
7451420 Determining reachable pins of a network of a programmable logic device  
A processor-implemented method is provided for determining reachable pins functionally connected to a network of a netlist that describes a programmable logic device (PLD) design. A netlist and an...
7451418 Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size  
Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated...
7451410 Stackable motherboard and related sensor systems  
The stackable motherboard 10 of the first embodiment includes: a circuit board 19 having a first side 14 and a second side 17 opposite the first side 14 , a processor 16 mounted on the...
7448015 Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation  
A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive...
7448014 Design stage mitigation of interconnect variability  
The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention,...
7448002 Inspection system  
An inspection system applicable to a data processing device installed with a PCB (printed circuit board) design software and a display unit is proposed, wherein the PCB design software is used for...
7444600 System and method for circuit noise analysis  
Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic...
7444424 Method and apparatus for routing data across an n-dimensional grid network  
One embodiment of the present invention provides a system for routing data between integrated circuit devices. This system couples together an n-dimensional grid of integrated circuit devices using...
7441223 Method and apparatus for performing synthesis to improve density on field programmable gate arrays  
A method for designing a system on a programmable logic device (PLD) includes implementing a first network of logic elements (LEs) and a second network of LEs with a combined network of LEs that...
7441220 Local preferred direction architecture, tools, and apparatus  
Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one...
7437699 Layout method for semiconductor integrated circuit, layout program for semiconductor integrated circuit and layout system for semiconductor integrated circuit  
When carrying out placement and routing processing on a layout object circuit using circuit connectivity information and power supply information, a first step of specifying a power supply terminal...
7437698 Method and program product for protecting information in EDA tool design views  
Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net...
7434198 Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction  
A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the...
7434191 Router  
Configuration of a reconfigurable multidimensional field may include prioritizing required connections between cells, establishing connections having a high priority first, and establishing...
7430730 Disabling unused IO resources in platform-based integrated circuits  
The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by...
7428720 Standard cell for a CAD system  
In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this...
7424695 Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit  
A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an...
7421673 Design checks for signal lines  
Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline...
7418693 System and method for analysis and transformation of layouts using situations  
Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout...
7418688 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit  
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the...
7415688 Method of manufacturing surface-emitting backlight, by molding contact member integrally with molded case  
A method of manufacturing a surface-emitting backlight is provided with the steps of forming a lead frame and resin-made molded case by insert molding, attaching light sources, which are red, blue...
7415687 Method and computer program for incremental placement and routing with nested shells  
A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and...
7412681 DC path checking in a hierarchical circuit design  
A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within...
7409664 Architecture and interconnect scheme for programmable logic circuits  
An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block...
7409663 Process for the production of an electrical wiring diagram  
This process allows for the automatic production of an electrical wiring diagram on which are located boxes, each representing a component used in an electrical device, connecting lines, each...
7409662 Systems and methods involving designing shielding profiles for integrated circuits  
A method for designing shielding in integrated circuits, the method comprising, receiving a first input designating a first net segment profile on a first level in an integrated circuit for...
7409659 System and method for suppressing crosstalk glitch in digital circuits  
A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk...
7408382 Configurable circuits, IC's, and systems  
Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is...
7406669 Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models  
A method of enabling CRPR in an ETM. In an exemplary embodiment, the method includes locating a plurality of clocks defined within a core. The method may also include determining if one of the...
7404166 Method and system for mapping netlist of integrated circuit to design  
The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in...
7404162 Buffering technique using structured delay skewing  
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design...
7404161 Fullchip functional equivalency and physical verification  
A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived...
7401317 Method and system for rapidly identifying silicon manufacturing defects  
The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first...
7401313 Method and apparatus for controlling congestion during integrated circuit design resynthesis  
The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing...
7401312 Automatic method for routing and designing an LSI  
According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be...
7401308 Timing analysis apparatus, timing analysis method, and computer product  
A timing analysis apparatus includes a data extracting unit that extracts objective circuit data concerning an objective circuit to become an objective of a timing analysis from layout data...
7398506 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing  
A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to...
7398499 Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design  
A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm,...
7398498 Method and apparatus for storing routes for groups of related net configurations  
Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to...
7398492 Rules and directives for validating correct data used in the design of semiconductor products  
A method to validate data used in a design of a semiconductor product. The method includes (a) reading resources of an application set defining the semiconductor product in a partially fabricated...
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