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7619521 |
RFID network configuration program
An RFID network design system comprising a website hosted on a host computer which generates and displays icons specifically directed to various RFID components of a RFID network on a computer...
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7617535 |
Infected electronic system tracking
Techniques for generating an access control list to block traffic from a network device infected by malware.
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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617465 |
Method and mechanism for performing latch-up check on an IC design
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then...
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7614033 |
Mask data preparation
The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to...
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7614026 |
Pattern forming method, computer program thereof, and semiconductor device manufacturing method using the computer program
A pattern of a desired size is formed on a semiconductor substrate by the following procedure. A property, including at least one of an aberration of an exposure device, a property of an...
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7614025 |
Method of placement for iterative implementation flows
A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty...
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7614024 |
Method to implement metal fill during integrated circuit design and layout
Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known...
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7610568 |
Methods and apparatus for making placement sensitive logic modifications
Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already...
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7607114 |
Designer's intent tolerance bands for proximity correction and checking
A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into...
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7607113 |
Wiring pattern determination method and computer program product thereof
A wiring pattern determination method and a computer program thereof comprise a step of moving positions of tentatively designed plated leads on an edge of a semiconductor package to the positions...
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7603640 |
Multilevel IC floorplanner
To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions...
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7600208 |
Automatic placement of decoupling capacitors
Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In...
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7600207 |
Stress-managed revision of integrated circuit layouts
Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout...
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7600205 |
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method
The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with...
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7596771 |
Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same
The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element...
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7590962 |
Design method and architecture for power gate switch placement
A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the...
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7590960 |
Placing partitioned circuit designs within iterative implementation flows
A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding...
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7590959 |
Layout system, layout program, and layout method for text or other layout elements along a grid
A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference...
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7590955 |
Method and system for implementing layout, placement, and routing with merged shapes
Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are...
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7587703 |
Layout determination method, method of manufacturing semiconductor devices, and computer readable program
A layout determination method determines a layout of semiconductor devices that are to be created on a substrate by carrying out an exposure process. The layout determination method determines a...
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7587695 |
Protection boundaries in a parallel printed circuit board design environment
Multiple users may simultaneously edit a shared area of a printed circuit board design. In order to prevent conflicts between multiple users, a user draws a protection border around a portion of...
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7587694 |
System and method for utilizing meta-cells
Exemplary systems and methods of laying out integrated circuits are disclosed. The systems include a layout application configured to place geometries in conformance with layout constraints...
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7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
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7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
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7581197 |
Relative positioning of circuit elements in circuit design
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
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7574685 |
Method, system, and article of manufacture for reducing via failures in an integrated circuit design
An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of...
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7574684 |
Design data creating method, design data creating apparatus and computer readable information recording medium
A design data creating method, for creating design data to which predetermined design constraint requirements are added, includes a display data converting step of converting input design...
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7574683 |
Automating power domains in electronic design automation
One or more portions of the design (e.g., components, channels, or portions thereof) can be assigned instances of one or more component power domains (CPDs). Assigning an instance of a CPD to a...
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7571420 |
Dynamic sampling with efficient model for overlay
The present invention describes a method including: determining field-clustering scheme; selecting initial sample plan; establishing initial model of overlay, the initial model of overlay...
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7571418 |
Simulation site placement for lithographic process models
A method and system for performing the method are provided for designing a mask layout that includes selecting simulation sites for optical proximity correction (OPC) or mask verification, prior to...
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7571410 |
Resonant tree driven clock distribution grid
An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein....
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7571397 |
Method of design based process control optimization
The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout...
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7568178 |
System simulation and graphical data flow programming in a common environment using wire data flow
Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various...
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7565638 |
Density-based layer filler for integrated circuit design
A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may...
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7562328 |
Navigation tool for connectors
A method for creating a tool for enhancing navigation through a schematic display of a netlist is provided. In the method, the display of the netlist is partitioned into multiple pages. A vector is...
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7562327 |
Mask layout design improvement in gate width direction
In a cell comprising an N well and a P well, a distance SP 04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to...
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7562326 |
Method of generating a standard cell layout and transferring the standard cell layout to a substrate
A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the...
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7562317 |
Multitasking circuit layout diagram silkscreen text handling method and system
A multitasking circuit layout diagram silkscreen text handling method and system is proposed, which is designed for use in conjunction with a computer platform that runs a CAD (Computer-Aided...
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7559044 |
Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit
An automatic design method of a semiconductor integrated circuit includes: increasing an interval between a plurality of wiring patterns provided on a chip region to relieve a density of the wiring...
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7559042 |
Layout evaluating apparatus
To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual...
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7555739 |
Method and apparatus for maintaining synchronization between layout clones
A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method...
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7549137 |
Latch placement for high performance and low power circuits
A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a...
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7546571 |
Distributed electronic design automation environment
PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate...
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7546559 |
Method of optimization of clock gating in integrated circuit designs
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for...
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7543263 |
Automatic trace shaping method
An automatic trace shaping method comprises the steps of: setting sets of coaxial equiangular octagons each having sides parallel with a predetermined reference line; performing a process for...
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7543262 |
Analog layout module generator and method
In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a...
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7543261 |
I/O planning with lock and insertion features
A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon...
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7543251 |
Method and apparatus replacing sub-networks within an IC design
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
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7542891 |
Method of correlating silicon stress to device instance parameters for circuit simulation
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard,...
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