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RE40597 Evaluation TEG for semiconductor device and method of evaluation  
An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodes 10 and 20 having different electrode widths...
7461366 Usage of a buildcode to specify layout characteristics  
A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells)....
7458055 Apparatus, system, method, and program for facilitating the design of electronic assemblies  
An apparatus, system, method, and program for facilitating the design of electronic assemblies include transmitting a user interface application to a user over a publicly-accessible global network....
7458054 Method for designing integrated circuit package and method for manufacturing same  
A new IC package 12 is designed as follows. That is, a circuit block 2 is omitted from an existing IC package 11 including a package 11 a having a circuit block 1 and the circuit block 2...
7458051 ECO cell for reducing leakage power  
A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line...
7454733 Interconnect-aware methodology for integrated circuit design  
An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The...
7454721 Method, apparatus and computer program product for optimizing an integrated circuit layout  
A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact...
7454720 Method for optimizing a layout of supply lines  
A method for optimizing a circuit layout is provided which optimizes a circuit layout as a result of utilizing unused tracks of the circuit layout to expand supply lines. In a first step, a circuit...
7451430 Apparatus and method for generating transistor model  
In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion...
7451429 Computer automated method for optimizing an integrated circuit pattern in a layout verification process  
A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks...
7451421 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies  
A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions,...
7448013 Method and apparatus for facilitating circuit design  
There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to effects of clock skew, each delay element...
7448012 Methods and system for improving integrated circuit layout  
In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control...
7448002 Inspection system  
An inspection system applicable to a data processing device installed with a PCB (printed circuit board) design software and a display unit is proposed, wherein the PCB design software is used for...
7444614 Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal  
A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the...
7444610 Visualizing hardware cost in high level modeling systems  
Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The...
7444600 System and method for circuit noise analysis  
Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic...
7441219 Method for creating, modifying, and simulating electrical circuits over the internet  
The present invention enables a user to create, modify, simulate and save an electrical circuit using an Internet browser over an Internet connection. The user can change the connectivity of the...
7437698 Method and program product for protecting information in EDA tool design views  
Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net...
7437688 Element routing method and apparatus  
A method is provided for designing a system including an element, wherein the element connects a plurality of components. First, a system design including the plurality of components is...
7434198 Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction  
A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the...
7434189 I/O driver power distribution method for reducing silicon area  
Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC...
7434185 Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data  
A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files...
7428719 Layout of network using parallel and series elements  
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network...
7428718 Enhanced incremental placement during physical synthesis  
A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at...
7428714 Line width error check  
A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line...
7426706 Synthesis strategies based on the appropriate use of inductance effects  
A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal...
7426461 Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities  
In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities...
7424699 Modifying sub-resolution assist features according to rule-based and model-based techniques  
Modifying sub-resolution assist features includes receiving a mask pattern for a photolithographic mask. The mask pattern includes main features, and the photolithographic mask is operable to...
7424690 Interconnect integrity verification  
A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using...
7424687 Method and apparatus for mapping design memories to integrated circuit layout  
A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated...
7418687 Information processing apparatus and information display method  
An information processing apparatus includes: an input unit; a storing unit configured to store wiring layout information and layer configuration information of a multilayer printed circuit board;...
7418686 System for representing the logical and physical information of an integrated circuit  
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by...
7418685 Layout method for miniaturized memory array area  
Bit lines and a pair of two tungsten wires having the same widths are formed at a portion where a through-hole is to be formed such that the bit lines and the tungsten wires are arranged at regular...
7415687 Method and computer program for incremental placement and routing with nested shells  
A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and...
7409667 Techniques for modeling a circuit board structure  
A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit board dimension parameters from a...
7409666 Automated PCB manufacturing documentation release package system and method  
An automated PCB manufacturing documentation release package system including a PCB database including PCB CAD data associated with a CAD file of a PCB design, and a shape engine configured to...
7409662 Systems and methods involving designing shielding profiles for integrated circuits  
A method for designing shielding in integrated circuits, the method comprising, receiving a first input designating a first net segment profile on a first level in an integrated circuit for...
7409661 Computer-aided thermal relief pad design system and method  
A computer-aided thermal relief pad design system includes a depicting unit, a memory unit and a calculating unit. The depicting unit is used for depicting an elongated oval pattern of a thermal...
7409651 Automated migration of analog and mixed-signal VLSI design  
A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source technology. The source circuit includes...
7405956 Line layout structure of semiconductor memory devices  
A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the...
7404161 Fullchip functional equivalency and physical verification  
A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived...
7401317 Method and system for rapidly identifying silicon manufacturing defects  
The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first...
7401312 Automatic method for routing and designing an LSI  
According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be...
7401311 Methodology for placement based on circuit function and latchup sensitivity  
A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element...
7401301 Circuit design support method, device thereof, and circuit design support program  
To enable automatic calculation of a circuit element value and a waveform by a computer. In a circuit design support for calculating a circuit element value of an analog electronic circuit to be...
7398506 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing  
A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to...
7398497 Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method  
An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general...
7398492 Rules and directives for validating correct data used in the design of semiconductor products  
A method to validate data used in a design of a semiconductor product. The method includes (a) reading resources of an application set defining the semiconductor product in a partially fabricated...
7392495 Method and system for providing hybrid clock distribution  
A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the...
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