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7620928 |
Method and apparatus for synthesizing a hardware system from a software description
A method and an apparatus take software source code to synthesize a hardware platform for running the software. The method determines which processor is suitable for running the code and meeting...
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7620917 |
Methods and apparatuses for automated circuit design
Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through...
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7620863 |
Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective...
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7620827 |
Methods and apparatus for cooling integrated circuits
A system and method are disclosed which may include measuring a leakage current level of a processor or multiprocessor chip; and storing an indicator value indicative of the leakage current level...
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7617471 |
Processor event interface for programmable integrated circuit based circuit designs
A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A...
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7617467 |
Electrostatic discharge device verification in an integrated circuit
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit;...
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7617264 |
Parallel remembered-set processing respecting popular-object detection
A garbage collector that operates in multiple threads divides a generation of a garbage-collected heap into heap sections, with which it associates respective remembered sets of locations where...
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7614025 |
Method of placement for iterative implementation flows
A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty...
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7614022 |
Testing for bridge faults in the interconnect of programmable integrated circuits
Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured...
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7614021 |
Optimal amplifier performance selection method
A method of determining an amplifier performance is provided. One embodiment establishes a number of amplifier performance constraints. A search is then conducted for an input and an output disk...
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7614020 |
Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems
A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns...
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7610572 |
Semiconductor integrated circuit device with independent power domains
A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an...
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7610569 |
Chip design verification apparatus and data communication method for the same
A method of verifying a chip design includes: a software side operation step of transmitting output data generated by an operation of a software block to an interface unit, determining whether...
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7607112 |
Method and apparatus for performing metalization in an integrated circuit process
A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that...
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7603647 |
Recognition of a state machine in high-level integrated circuit description language code
A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as...
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7603645 |
Calibration method of insulating washer in circuit board
A calibration method of insulating washer in a circuit board is provided, which includes steps of (a) establishing an equivalent circuit model corresponding to a metal via; (b) depicting an...
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7603639 |
Method, apparatus and computer program product for controlling jitter or the effects of jitter in integrated circuitry
Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first...
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7603638 |
Method and system for modeling statistical leakage-current distribution
Disclosed is a method and system for modeling statistical leakage current distribution using logarithmic skew-normal distribution by generating statistical data with a statistical analysis method...
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7603635 |
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same
A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The...
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7603634 |
Various methods and apparatuses to preserve a logic state for a volatile latch circuit
An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state...
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7603579 |
Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another
A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the...
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7600211 |
Toggle equivalence preserving logic synthesis
A method of synthesis of a second circuit (N 2 ) that is toggle equivalent to a first circuit (N 1 ), comprising building up N 2 in topological order, starting from the input side of N 2 , by...
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7600204 |
Method for simulation of negative bias and temperature instability
An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned...
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7600202 |
Techniques for providing a failures in time (FIT) rate for a product design process
A technique for providing a product FIT rate is performed within electronic circuitry (e.g., one or more computerized devices). The technique involves receiving a Mean Time To Failure (MTTF) target...
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7596772 |
Methodology and system for setup/hold time characterization of analog IP
A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The...
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7596482 |
System and method to analyze and determine ampacity risks on PCB interconnections
Determining ampacity risks in a circuit comprises receiving geometry data of the circuit, initializing boundary conditions, initializing circuit geometry assumptions, modeling the circuit geometry...
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RE40925 |
Methods for automatically pipelining loops
A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level...
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7594211 |
Methods and apparatuses for reset conditioning in integrated circuits
Embodiments of the present invention disclose methods and apparatuses to reduce metastability problem related to propagation delay of reset signals in integrated circuits, with preferred...
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7594198 |
Ultra fine pitch I/O design for microchips
A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a...
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7594197 |
Semiconductor device having predictable electrical properties
A circuit element of a semiconductor device is provided. The circuit element has an electrical property and is formed by at least two like individual elements, each of said individual elements...
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7594196 |
Block interstitching using local preferred direction architectures, tools, and apparatus
Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by...
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7594195 |
Multithreaded reachability
In one embodiment, a method for multithreaded reachability analysis includes partitioning a state space of a circuit under analysis into a plurality of partitions and assigning each partition to a...
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7590967 |
Structured ASIC with configurable die size and selectable embedded functions
One embodiment of the present invention provides for a master or universal base and base tooling which addresses the general purpose Structured ASIC requirements. Another embodiment of the present...
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7590963 |
Integrating multiple electronic design applications
Multiple printed circuit board (PCB) application programs simultaneously execute on a computer. Each application stores data regarding a PCB design in a separate database. The databases are based...
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7590955 |
Method and system for implementing layout, placement, and routing with merged shapes
Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are...
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7590952 |
Compact chip package macromodels for chip-package simulation
A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance...
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7590951 |
Plug-in component-based dependency management for partitions within an incremental implementation flow
A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and,...
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7587693 |
Apparatus and method of delay calculation for structured ASIC
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a...
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7587686 |
Clock gating in a structured ASIC
Circuits and methods use clock gating to reduce power consumption in select parts of a structured ASIC. A clock distribution network includes a deterministic portion, a configurable portion, and...
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7584447 |
PLD architecture for flexible placement of IP function blocks
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function...
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7584446 |
Method and apparatus for extending processing time in one pipeline stage
A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each...
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7584443 |
Clock domain conflict analysis for timing graphs
The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while...
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7584437 |
Assuring correct data entry to generate shells for a semiconductor platform
A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated...
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7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
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7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
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7581197 |
Relative positioning of circuit elements in circuit design
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
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7577932 |
Gate modeling for semiconductor fabrication process effects
In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic...
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7577927 |
IC design modeling allowing dimension-dependent rule checking
A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core...
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7577926 |
Security-sensitive semiconductor product, particularly a smart-card chip
To provide a security-sensitive semiconductor product, particularly a smartcard chip, in which are produced not only electrically active structures ( 2, 3, 4, 5, 6 ) envisaged by the chip design in...
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7577558 |
System and method for providing compact mapping between dissimilar memory systems
A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one...
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