|
Match
|
Document |
Document Title |
|
|
7487479 |
Systematic approach for applying recommended rules on a circuit layout
A method and apparatus for enforcing design for manufacturability rules on a circuit layout is provided. A tool receives a first set of design rules, to be applied to the circuit layout, which must...
|
|
|
7487473 |
Enabling netlist for modeling of technology dependent BEOL process variation
A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one...
|
|
|
7487481 |
Receiver circuit for on chip timing adjustment
A structure for for maintaining signal integrity between integrated circuits residing on a printed circuit board. The structure has adjustable delay circuitry within the circuits and the adjustable...
|
|
|
7483913 |
XML-based system and method for collaborative web-based design and verification of system-on-a-chip
A computer-based design framework for collaborative design of a product by distributed design team members. The design framework comprises: a virtual database management system, which receives data...
|
|
|
7484186 |
Method for designing a system LSI
A method for designing a system LSI includes the step of defining, for each of instructions of the processor, a behavior function description and an instruction description specifying the behavior...
|
|
|
7484193 |
Method and software for predicting the timing delay of a circuit path using two different timing models
The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models...
|
|
|
7480610 |
Software state replay
A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for...
|
|
|
7480888 |
Design structure for facilitating engineering changes in integrated circuits
A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations...
|
|
|
7480875 |
Method of designing a semiconductor integrated circuit
In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while...
|
|
|
7480605 |
Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty
Techniques are disclosed for determination of parameter variability for one or more given interconnects of a plurality of interconnects in a simulated semiconductor circuit. The simulated...
|
|
|
7480874 |
Reliability analysis of integrated circuits
Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance...
|
|
|
7478344 |
Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms
A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a...
|
|
|
7478027 |
Systems, methods, and media for simulation of integrated hardware and software designs
Systems, methods and media for simulation of integrated hardware and software designs are disclosed. More particularly, hardware and/or software for synchronizing cycle timers of an integrated...
|
|
|
7478357 |
Versatile bus interface macro for dynamically reconfigurable designs
Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable...
|
|
|
7478345 |
Apparatus and method for measuring characteristics of dynamic electrical signals in integrated circuits
Systems and methods consistent with principles of the present invention allow contactless measurements of voltage characteristics of dynamic electrical signals in integrated circuits. The invention...
|
|
|
7478355 |
Input/output circuits with programmable option and related method
A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a...
|
|
|
7478353 |
Non-uniform decoupling capacitor distribution for uniform noise reduction across chip
An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged...
|
|
|
7478346 |
Debugging system for gate level IC designs
A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump...
|
|
|
7478351 |
Designing system and method for designing a system LSI
A method for designing a system LSI includes the steps of dividing an algorithmic description (D 1 ) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior...
|
|
|
7475381 |
Shallow trench avoidance in integrated circuits
Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.
|
|
|
7475366 |
Integrated circuit design closure method for selective voltage binning
Disclosed are embodiments of a method of designing and producing an integrated circuit. During the pre-release chip design process, the method subdivides the overall process window for an...
|
|
|
7475000 |
Apparatus and method for managing integrated circuit designs
Apparatus and methods for integrated circuit (IC) design, including management of the configuration, design parameters, and functionality of a design in which custom instructions or other design...
|
|
|
7475372 |
Methods for computing Miller-factor using coupled peak noise
A method for computing a Miller-factor compensated for peak noise provided. The method includes mapping at least two delays as function of at least two Miller-factors; determining an equation of...
|
|
|
7475373 |
Method and apparatus to visually assist legalized placement with non-uniform placement rules
Embodiments of the present invention provide systems, methods and articles of manufacture for displaying semiconductor components in a graphical user interface and manipulating the position of...
|
|
|
7471116 |
Dynamic constant folding of a circuit
The present invention provides a method involving at least one first circuit having at least one first input, at least one second input, and at least one output. The method includes determining at...
|
|
|
7472365 |
Method for computing hold and setup slack without pessimism
The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not...
|
|
|
7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
|
|
|
7472358 |
Method and system for outputting a sequence of commands and data described by a flowchart
The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of...
|
|
|
7472361 |
System and method for generating a plurality of models at different levels of abstraction from a single master model
A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that...
|
|
|
7469399 |
Semi-flattened pin optimization process for hierarchical physical designs
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of...
|
|
|
7469389 |
Standard cell library, method of designing semiconductor integrated circuit, semiconductor integrated circuit pattern, and semiconductor integrated circuit
An exemplary cell library includes a first plurality of types of standard cells. Each of the first plurality of types of standard cells includes threshold voltage adjusting patterns. The upper and...
|
|
|
7467358 |
Asynchronous switch based on butterfly fat-tree for network on chip application
The present invention disclosed herein is an asynchronous switch for an network on chip application making possible between IP (Intellectual Property) communication among various IPs in the network...
|
|
|
7467360 |
LSI design support apparatus and LSI design support method
An LSI design support apparatus includes a data acquisition section and an equal processing section. The data acquisition section acquires first position data concerning positions of a plurality of...
|
|
|
7467359 |
Decoder using a memory for storing state metrics implementing a decoder trellis
A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit,...
|
|
|
7467367 |
Method and system for clock tree synthesis of an integrated circuit
Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit....
|
|
|
7467077 |
Mesh model creating method, simulation apparatus and computer-readable storage medium
A mesh model creating method includes a mesh forming step to divide a region that is a target of a simulation into a plurality of polygonal meshes so that each node within the region is positioned...
|
|
|
7464346 |
Method for designing phase-lock loop circuits
A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit...
|
|
|
7464360 |
Common interface framework for developing field programmable device based applications independent of a target circuit board
A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD)....
|
|
|
7464361 |
System and method for asynchronous logic synthesis from high-level synchronous descriptions
A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior.
|
|
|
7464350 |
Method of and circuit for verifying a layout of an integrated circuit device
A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated...
|
|
|
7464357 |
Integrated circuit capable of locating failure process layers
An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is...
|
|
|
7464345 |
Resource estimation for design planning
A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the...
|
|
|
7464352 |
Methods for designing, evaluating and manufacturing semiconductor devices
A semiconductor device 100 has a configuration having a via 124 formed on a first interconnect 112 . A method for designing the semiconductor device 100 includes: calculating an anticipated...
|
|
|
7464347 |
Method for collaboration of issue-resolution by different projects in a processor design
This invention is a toolset upgrading the basic WEBS system update that facilitates tracking design bugs. This invention provides an effective means for reporting, tracking, and eliminating design...
|
|
|
7461366 |
Usage of a buildcode to specify layout characteristics
A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells)....
|
|
|
7461360 |
Validating very large network simulation results
A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws...
|
|
|
7460986 |
System DC Analysis Methodology
A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a...
|
|
|
7461359 |
Method and mechanism for determining shape connectivity
A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of...
|
|
|
7458040 |
Resettable memory apparatuses and design
Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of...
|
|
|
7458049 |
Aggregate sensitivity for statistical static timing analysis
A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution...
|