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7516434 Layout design program, layout design device and layout design method for semiconductor integrated circuit  
A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to...
7512908 Method and apparatus for improving SRAM cell stability by using boosted word lines  
The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage...
7512915 Embedded test circuit for testing integrated circuits at the die level  
A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing...
7512912 Method and apparatus for solving constraints for word-level networks  
The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is...
7512907 Generating rules for nets that cross package boundaries  
In an embodiment, data models are stitched into a stitched data model, where each of the data models has nets and at least one of the nets crosses a package boundary. A subset of the nets from the...
7512921 Method and apparatus for designing integrated circuit enabling the yield of integrated circuit to be improved by considering random errors  
A layout method in a layout apparatus for layout of an integrated circuit includes placing a plurality of cells at approximate positions according to the circuit data and placing the plurality of...
7512909 Read strobe feedback in a memory system  
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct...
7509594 Method of selling integrated circuit dies for multi-chip packages  
An integrated circuit has a plurality of bonding pads, at least one of which is adapted to be directly electrically connected to a bonding pad of another integrated circuit rather than to an...
7509595 Method and system for enabling energy efficient wireless connectivity  
An apparatus and method that enables several different factors associated with the implementation of a particular wireless application to be considered in the design of an energy efficient wireless...
7509603 Semiconductor integrated circuit and design method thereof  
A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of logic blocks each of which is...
7509596 Power distribution network simulation method using variable reduction method  
A power distribution network simulation method capable of speedily and accurately analyzing a large power distribution network. In the power distribution network simulation method, the large...
7509247 Electromagnetic solutions for full-chip analysis  
A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may...
7509607 Memory circuit having a crosstalk-glitch suppressor circuit and a control device for controlling an amount of suppression performed by the crosstalk-glitch suppressor circuit  
The memory circuit comprises: a single or a plurality of reading-out port(s); a single or a plurality of writing port(s); a crosstalk-glitch suppressor circuit for suppressing crosstalk glitch...
7509599 Method and apparatus for performing formal verification using data-flow graphs  
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM DFG and HLM DFG . RTLM DFG and HLM DFG are then put into...
7509612 Method of designing semiconductor chip and program for use in designing semiconductor chip  
Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same...
7509619 Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages  
A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein...
7509618 Method and apparatus for facilitating an adaptive electronic design automation tool  
A method for designing systems on field programmable gate arrays (FPGAs) includes caching design information from a compilation of a system design. The design information is utilized in a...
7506277 Method and mechanism for implementing DFM aware cells for an electronic design  
An improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and...
7506294 Incremental solver for modeling an integrated circuit  
A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for...
7506287 Method, system, and program product for pre-compile processing of hardware design language (HDL) source files  
A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded...
7506276 Method for isolating problem networks within an integrated circuit design  
A method of modifying an integrated circuit design. A noise threshold is determined. A threshold, noisy wire length for a particular integrated circuit design is selected. An integrated circuit...
7506279 Design supporting apparatus capable of checking functional description of large-scale integrated circuit to detect fault in said circuit  
A design supporting apparatus is disclosed, including: an inputting part; a syntactic analyzing part; and a scanning and searching part. The inputting part inputs functional description data of a...
7506296 Programmable logic device design tool with support for variable predriver power supply levels  
A logic design system is provided for designing programmable logic device integrated circuits with minimized predriver power consumption. The logic design system identifies predriver circuits that...
7503019 Point and click expression builder  
In one embodiment, a method for constructing an application includes presenting to a user a list of possible elements for a logic expression. The possible elements may include one or more names of...
7503027 Hardware description language code generation from a state diagram  
The present invention provides a state diagramming environment in a computing device that enables the conversion of a state diagram into a hardware description language. To achieve this conversion,...
7502721 Product design support system, product design support method, and program  
A product design support system comprises a product design support server ( 1 ), a product design support database ( 2 ) where parts information, parts image information, circuit information and...
7503017 Method and program for library generation  
A library generation device determines a characteristic approximation function based on a characteristic extraction table to calculate characteristic data corresponding to a client's conditions in...
7503018 Method of switching a power supply of voltage domains of a semiconductor circuit, and corresponding semiconductor circuit  
A method of switching a power supply of at least one voltage domain of a semiconductor circuit uses at least one microswitch, which is designed in standard cell design, to switch the power supply,...
7500207 Influence-based circuit design  
An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the...
7500228 System and method for automatically generating a hierarchical register consolidation structure  
A system for, and method of, automatically generating a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a graph generator that parses a High-level Design...
7500206 Delay time verifying method with less processing load  
In a method of verifying a delay time of a target circuit section, a first determination of a shortest of short delay times of each of components of the target circuit section in two or more...
7496872 Library creating device and interconnect capacitance estimation system using the same  
An interconnect capacitance estimation system includes a first storage device, a library creating device and an interconnect capacitance estimating device. The first storage device stores layout...
7496862 Method for automatically modifying integrated circuit layout  
This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations...
7496870 Method of selecting cells in logic restructuring  
The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The...
7496871 Mutual inductance extraction using dipole approximations  
Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal...
7496869 Method and apparatus for implementing a program language description of a circuit design for an integrated circuit  
Method and apparatus for implementing a program language description of a circuit design for an integrated circuit is described. In one example, a program is specified using a concurrent...
7496861 Method for generalizing design attributes in a design capture environment  
A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of...
7496877 Electrostatic discharge failure avoidance through interaction between floorplanning and power routing  
An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits...
7496864 Interactive loop configuration in a behavioral synthesis tool  
A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information...
7496866 Method for optimizing of pipeline structure placement  
Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These...
7496875 Designing method for designing electronic component  
A designing method for designing an electronic component aiming at increase in designing efficiency is provided. The designing method has a step of setting a predetermined electrical...
7496863 Nonlinear driver model for multi-driver systems  
A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by...
7496874 Semiconductor yield estimation  
A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant...
7493240 Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithm  
Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The...
7493576 CDM ESD event protection in application circuits  
Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note...
7493578 Correlation of data from design analysis tools with design blocks in a high-level modeling system  
Methods are provided for processing design information of an electronic circuit design. A single path or multiple paths that are produced by a first design tool are an input for the method. Each...
7493574 Method and system for improving yield of an integrated circuit  
Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to...
7493587 Chromeless phase shifting mask for integrated circuits using interior region  
A system for creating mask layout pattern data in order to create a number of desired features on a semiconductor wafer. Critical features and features that are adjacent to or abut critical...
7490302 Power gating various number of resources based on utilization levels  
Power-gating circuit resources of an integrated circuit is described. The circuit resources are associated into sets responsive to utilization levels. The associating includes providing a first set...
7487472 Method, system and program product for synchronous communication between a public electronic environment and a private electronic environment  
Synchronous communications between a public electronic environment (e.g., a browser on a global computer network) and a private electronic environment (e.g., an ERP application on a private...
Matches 151 - 200 out of 1609 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >