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7546571 Distributed electronic design automation environment  
PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate...
7546562 Physical integrated circuit design with uncertain design conditions  
In one embodiment of the invention, a physical integrated circuit (IC) design tool is provided including a design uncertainties file, a user interface (UI) software module, and a design analysis...
7546556 Virtual shape based parameterized cell  
A method of designing an electric circuit includes generating a part of the design, determining a virtual shape based on the part, and using the virtual shape to generate a design for an additional...
7546566 Method and system for verification of multi-voltage circuit design  
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage...
7543250 On-chip packet-based interconnections using repeaters/routers  
In some embodiments, multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which...
7543259 Method and device for deciding support portion position in a backup device  
A host computer 80 for wholly controlling an electronic component mounting line displays a surface side image and a reverse side image which respectively show a surface side and a reverse side of...
7543249 Embedded switchable power ring  
An integrated circuit comprises an embedded switchable power ring for supplying power to circuit modules ( 15.1, . . . , 15.5 ) arranged within the switchable power ring ( 13 ). The switchable...
7543252 Migration of integrated circuit layout for alternating phase shift masks  
Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to...
7543253 Method and apparatus for compensating for temperature drift in semiconductor processes and circuitry  
The present invention provides a method and apparatus for compensating for temperature effects in the operation of semiconductor processes circuitry, such as reference circuits. The method operates...
7543258 Clock design apparatus and clock design method  
A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust...
7543251 Method and apparatus replacing sub-networks within an IC design  
Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this...
7539957 Automatic test pattern generation tool with feedback path capabilities for testing circuits with repeating blocks  
Methods and apparatus for testing integrated circuits are provided. Integrated circuits sometimes contain repeating blocks of identical circuitry. Each identical circuit block contains scan chain...
7539956 System and computer program product for simultaneous cell identification/technology mapping  
A system, method and computer program product are provided for simultaneous cell identification/technology mapping. In use, a plurality of data operators is received. Further, at least two cells...
7539953 Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system  
Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is...
7539952 Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit  
A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a...
7539959 Library creating apparatus and method, and recording medium recording library creating program thereon  
In order to efficiently create a library of characteristic values of a low hierarchical circuit, which library is used in operation verification of circuitry including low hierarchical circuitry...
7536669 Generic DMA IP core interface for FPGA platform design  
A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as...
7536658 Power pad synthesizer for an integrated circuit design  
A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two...
7536659 Semiconductor memory device and semiconductor device  
Decreases in area efficiency and wiring efficiency and degradation in performance are prevented which result from imbalances in dimensional ratios between miniaturized control circuits and other...
7531368 In-line lithography and etch system  
The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer...
7530032 Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junctions  
Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the...
7530044 Method for manufacturing a programmable system in package  
Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies several...
7529858 Hard disk drive controller having versatile chip connector having printed circuit board engaged by at least two data ports having two pairs of differential connector elements  
A hard disk controller (HDC) chip has interchangeable “A” and “B” ports of differential connector element pairs, with one connector element of each pair being disposed closest to the edge...
7530033 Method and apparatus for decomposing functions in a configurable IC  
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output...
7530034 Apparatus and method for circuit operation definition  
A method and apparatus for defining a circuit operation, such as a charged particle beam operation to perform a circuit edit and define a probe point. Circuit operation definition is performed in a...
7526740 System and method for automated electronic device design  
A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher...
7526419 Methods for reconstructing data from simulation models  
Methods for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a...
7526739 Methods and systems for computer aided design of 3D integrated circuits  
Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a...
7523420 Degeneration technique for designing memory devices  
A system, method and computer program product are provided for producing an instance of a memory device from a banked memory architecture. The banked memory architecture specifies a maximum number...
7523424 Method and system for representing analog connectivity in hardware description language designs  
System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have...
7523434 Interfacing with a dynamically configurable arithmetic unit  
An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for...
7523419 Semiconductor integrated device for preventing breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof, design method thereof, designing apparatus method thereof, and maunfacturing apparatus thereof  
Semiconductor integrated circuit that prevents breakdown and degradation of a gate oxide film caused by charge-up in manufacturing steps thereof is provided. The circuit includes a gate 12 ...
7519926 Semiconductor device and method for designing the same  
Disclosed is a method for designing a semiconductor device so as to prevent the device from being broken even when memory circuits are reset. This method is executed using a computer as follows....
7519930 Method of calculating a model formula for circuit simulation  
A circuit simulator for a semiconductor device with reduced channel length includes a method of calculating a model formula for circuit simulation of a semiconductor device; calculating first...
7519939 Method and program for supporting register-transfer-level design of semiconductor integrated circuit  
A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a...
7519927 Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations  
Wiring structures and methods for integrated circuit designs which are adapted to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle time overlap violations in...
7519925 Integrated circuit with dynamically controlled voltage supply  
An electronic system ( 10 ). The system comprises circuitry (P 1 ) for receiving a system voltage from a voltage supply. The system also comprises circuitry ( 14 1 ), responsive to the system...
7519935 Circuit diagram drafting system and method and computer program product  
A circuit diagram drafting system for drafting a circuit diagram comprised of a plurality of circuit components and connections connecting terminals of the circuit components, the circuit diagram...
7519937 Circuit diagram processing system and method  
A data processing system and method is proposed. The data processing system is connected with a component library and an original design database. The component library includes component data...
7516428 Microwave circuit performance optimization by on-chip digital distribution of operating set-point  
A method and circuit are outlined allowing the performance of an RF circuit to be established through the use of digital calibration data, which is stored within a programmable memory store and...
7516430 Generating testcases based on numbers of testcases previously generated  
A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or...
7516424 Modeling and simulating a powergated hierarchical element  
A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does...
7516426 Methods of improving operational parameters of pair of matched transistors and set of transistors  
Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at...
7516425 Method for generating minimal leakage current input vector using heuristics  
A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics includes transforming the integrated circuit to a logic representation with PMOS...
7516436 Method for manufacturing a power bus on a chip  
A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a...
7516423 Method and apparatus for designing electronic circuits using optimization  
Methods and apparatus for designing electronic circuits, including analog and mixed signal (AMS) circuits, based on an evolutionary optimization approach. In one exemplary embodiment, the...
7516434 Layout design program, layout design device and layout design method for semiconductor integrated circuit  
A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to...
7512908 Method and apparatus for improving SRAM cell stability by using boosted word lines  
The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage...
7512915 Embedded test circuit for testing integrated circuits at the die level  
A design structure instantiated in a machine readable medium; the design structure includes all of the necessary information for designing a test circuit. The test circuit is used for performing...
7512912 Method and apparatus for solving constraints for word-level networks  
The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is...
Matches 101 - 150 out of 1605 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >