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7584446 |
Method and apparatus for extending processing time in one pipeline stage
A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each...
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7584443 |
Clock domain conflict analysis for timing graphs
The present invention is directed to clock domain conflict analysis of a timing graph that features, dissociating clock domains of one or more of a path having conflicting clock domains while...
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7581200 |
System and method for analyzing length differences in differential signal paths
A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device ( 9 ); simulating the differential...
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7581197 |
Relative positioning of circuit elements in circuit design
Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed,...
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7581198 |
Method and system for the modular design and layout of integrated circuits
An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of...
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7577926 |
Security-sensitive semiconductor product, particularly a smart-card chip
To provide a security-sensitive semiconductor product, particularly a smartcard chip, in which are produced not only electrically active structures ( 2, 3, 4, 5, 6 ) envisaged by the chip design in...
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7577927 |
IC design modeling allowing dimension-dependent rule checking
A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core...
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7577558 |
System and method for providing compact mapping between dissimilar memory systems
A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one...
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7577932 |
Gate modeling for semiconductor fabrication process effects
In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic...
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7574679 |
Generating cores using secure scripts
Methods and apparatus are provided for securely generating IP cores. A designer selects and configures parameterizable IP cores provided for implementation on a programmable chip. The IP cores are...
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7574680 |
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory...
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7574681 |
Method and system for evaluating computer program tests by means of mutation analysis
Methods and systems for evaluating computer program tests by mutation analysis, including the execution of mutated programs with the insertion of mutations and the identification of mutated...
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7571404 |
Fast on-chip decoupling capacitance budgeting method and device for reduced power supply noise
A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network...
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7571396 |
System and method for providing swap path voltage and temperature compensation
The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes...
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7571401 |
Calculating distortion summaries for circuit distortion analysis
Methods for analyzing circuit distortion based on contributions from separate circuit elements are presented. Local approximations that do not require high-order derivatives of device models are...
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7571395 |
Generation of a circuit design from a command language specification of blocks in matrix form
Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands...
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7568178 |
System simulation and graphical data flow programming in a common environment using wire data flow
Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various...
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7567893 |
Clock simulation system and method
A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock...
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7568172 |
Integration of pre-defined functionality and a graphical program in a circuit
System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in...
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7565631 |
Method and system for translating software binaries and assembly code onto hardware
A computer-aided hardware design system enables design of an actual hardware implementation for a digital circuit using a software implementation of an algorithm in assembly language or machine...
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7565632 |
Behavioral synthesizer system, operation synthesizing method and program
A behavioral synthesis system which synthesizes behavior without inline expansion of a callee function, even one which has a pointer as an argument during the synthesis of a caller function. There...
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RE40855 |
Integrated circuit having a reduced spacing between a bus and adjacent circuitry
An integrated circuit that reduces spacing between circuitry and a bus. In accordance with this invention, the bus is a strip of conductive material in a layer of the integrated circuit. The layer...
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7562335 |
Semiconductor device and method of testing the same
An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of...
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7562317 |
Multitasking circuit layout diagram silkscreen text handling method and system
A multitasking circuit layout diagram silkscreen text handling method and system is proposed, which is designed for use in conjunction with a computer platform that runs a CAD (Computer-Aided...
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7562336 |
Contrast based resolution enhancement for photolithographic processing
A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to...
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7562322 |
Design verification for a switching network logic using formal techniques
Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the...
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7562315 |
Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an...
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7562316 |
Apparatus for power consumption reduction
A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block...
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7562320 |
Asic based conveyor belt style programmable cross-point switch hardware accelerated simulation engine
An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication...
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7562324 |
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew...
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7562332 |
Disabling unused/inactive resources in programmable logic devices for static power reduction
A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic...
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7562237 |
Semiconductor integrated circuit device with internal power control system
One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the...
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7562318 |
Test structure for automatic dynamic negative-bias temperature instability testing
The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI)....
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7562321 |
Method and apparatus for structured ASIC test point insertion
Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the...
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7559041 |
Method and apparatus for designing semiconductor integrated circuit
A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit...
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7558969 |
Anti-pirate circuit for protection against commercial integrated circuit pirates
Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that...
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7559032 |
System and method for enabling a graphical program to respond to user interface events
A system and method for enabling a graphical program to receive and respond to programmatic events. The graphical program may include a graphical user interface having various user interface...
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7559040 |
Optimization of combinational logic synthesis through clock latency scheduling
In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in...
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7559045 |
Database-aided circuit design system and method therefor
A database-aided circuit design system and method therefor is provided, which can be utilized to detect problems of the product in an early design stage through the early design stage...
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7555733 |
Hierarchical partitioning
Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several...
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7555735 |
IC design modeling allowing dimension-dependent rule checking
A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core...
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7555734 |
Processing constraints in computer-aided design for integrated circuits
A computer-implemented method of performing a Computer-Aided Design (CAD) flow on a circuit design for a programmable logic device (PLD) can include inserting a preprocessing task into the CAD flow...
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7552404 |
Semiconductor integrated device and apparatus for designing the same
A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground...
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7552040 |
Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times....
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7549135 |
Design methodology of guard ring design resistance optimization for latchup prevention
A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS...
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7549133 |
System and method for qualifying a logic cell library
A system and a method for qualifying a logic cell library storing process parameters and properties of a specific semiconductor FAB when the logic cell library is newly developed or modified is...
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7546558 |
Method and apparatus for determining a process model that uses feature detection
One embodiment can provide a system for determining a process model that models an effect of one or more semiconductor manufacturing processes. During operation, the system can receive a test...
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7546557 |
Systems and methods for reducing IR-drop noise
The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The...
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7546559 |
Method of optimization of clock gating in integrated circuit designs
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for...
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7546564 |
Method for verifying optical proximity correction using layer versus layer comparison
A method for verifying optical proximity correction (OPC) using a layer-versus-layer (LVL) comparison. The method includes performing optical proximity correction of an original design of a...
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