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7076575 |
Method and system for efficient access to remote I/O functions in embedded control environments
A method for accessing I/O devices in embedded control environments is provided, wherein said I/O devices are remotely attached to an embedded microprocessor. By mapping said I/O devices' resources...
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7076745 |
Semiconductor integrated circuit device
The present invention provides a semiconductor integrated circuit device easy to design timing to be provided with respect to an external memory. In the semiconductor integrated circuit device ( 10...
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7075179 |
System for implementing a configurable integrated circuit
The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC...
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7076405 |
Method for estimating power consumption and noise levels of an integrated circuit, and computer-readable recording medium storing a program for estimating power consumption and noise levels of an integrated circuit
The present invention is related to a method for estimating power consumption and noise levels of an integrated circuit which is composed of logic gates connected in the form of a plurality of...
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7076748 |
Identification and implementation of clock gating in the design of integrated circuits
Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The...
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7073156 |
Gate estimation process and method
A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design...
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7073146 |
Method for clock synchronization validation in integrated circuit design
Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit...
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7073139 |
Method for determining cell body and biasing plate contact locations for embedded dram in SOI
A method for determining contact location for embedded dynamic random access memory (eDRAM) formed in a silicon-on-insulator (SOI) substrate includes reviewing contact design data for an eDRAM...
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7069095 |
System and method for populating a computer-aided design program's database with design parameters
According to at least one embodiment, a method comprises generating a data file having design parameters for an electrical design, and with a computer-executable program, accessing the data file...
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7069525 |
Method and apparatus for determining characteristics of MOS devices
A set of ring oscillators is formed within a predetermined distance of each other. Each ring oscillator includes a number of coupled stages. The stages for a first given ring oscillator include an...
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7069522 |
Various methods and apparatuses to preserve a logic state for a volatile latch circuit
Various methods and apparatuses are described in which a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch...
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7065720 |
Apparatus and methods for current-based models for characterization of electronic circuitry
A system for characterizing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input and output. The computer is configured to supply a stimulus to the...
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7065732 |
Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane
A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is...
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7065719 |
Method for designing a system LSI
A method for designing a system LSI includes the step of defining, for each of instructions of the processor, a behavior function description and an instruction description specifying the behavior...
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7062427 |
Batch editor for netlists described in a hardware description language
A system and method are disclosed for editing netlists described in a hardware description language (HDL). In one embodiment, a netlist is provided and a changes module is provided. The changes...
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7062726 |
Method for generating tech-library for logic function
The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the...
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7062728 |
Method of designing a logic circuit utilizing an algorithm based in C language
An algorithm C description describing an algorithm of computation or control of a logic circuit in a C language is split into a plurality of states in units of processing, and the execution order...
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7062725 |
Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit
A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is...
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7062727 |
Computer aided design systems and methods with reduced memory utilization
Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a...
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7062738 |
Flash memory compiler with flexible configurations
This invention provides a compiler, circuits and a method for generating a flash memory for integrated circuits. This invention provides a flash memory compiler which can generate flexible...
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7062741 |
Wire bond padring bond pad checker program
A computer-implemented method is described for verifying bond pad position conformity with predetermined design rules corresponding to a padring design. The padring design includes a plurality of...
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7058916 |
Method for automatically sizing and biasing circuits by means of a database
In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell...
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7058922 |
Semiconductor integrated circuit and method of manufacturing the same
A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction...
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7058906 |
Architecture for a sea of platforms
The present invention is directed to platform architecture used for integrated circuit design. A system for providing distributed dynamic functionality in an electronic environment may include a...
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7055112 |
Method for automatically defining a part model for semiconductor components
The present invention provides a method for automatically defining a part model for a semiconductor component. An image of the component is provided. The automatic method may be any of a trial and...
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7055115 |
Line width check in layout database
A method of performing a design rule check on an integrated circuit includes tagging at least one line in a schematic with a width marker and an associated width parameter, extracting the line...
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7055113 |
Simplified process to design integrated circuits
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification...
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7055124 |
System and method for evaluating signal deviations in a package design
A method is provided for evaluating signal deviations in an electronic design (e.g., a package design), including the steps of: formulating one or more signal deviation rules; processing the...
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7051306 |
Managing power on integrated circuits using power islands
Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled...
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7051294 |
Cold clock power reduction
A multi-mode latch timing circuit has a first set of latches and a second set of latches in each logical path. In a first mode of operation, first and second phase clock signals are provided so...
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7051313 |
Automatic generation of programmable logic device architectures
An “architecture generation engine” is operative with a CAD system to implement circuits into PLD (programmable logic device) architectures and to evaluate performances of different...
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7051314 |
Method of computer-assisted design of integrated circuit chips, and library of delay time values for computer-assisted design of such chips
A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from...
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7051293 |
Method and apparatus for creating an extraction model
A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and...
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7051296 |
Method and apparatus for parallel carry chains
An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within...
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7050874 |
Sourcing of bills of materials
A bill of materials (BOM) sourcing system includes one or more data storage locations that store BOM sourcing criteria. The system also includes a sourcing engine that receives a BOM that includes...
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7050871 |
Method and apparatus for implementing silicon wafer chip carrier passive devices
Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package....
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7047372 |
Managing I/O accesses in multiprocessor systems
A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is...
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7047173 |
Analog signal verification using digital signatures
A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or...
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7047514 |
Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign
An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a...
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7047511 |
Electronic circuit design
A method, system, program product and database for electronic circuit design configured to reduce data storage and computer resource requirements. The invention is binary based and leverages the...
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7043703 |
Architecture and/or method for using input/output affinity region for flexible use of hard macro I/O buffers
An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be...
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7043707 |
Simulation result verification method and simulation result verification device
A simulation result verification method of the present invention compares a simulation result representing the relationship between the time and the output state at a given node, with condition...
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7039576 |
System verification equipment, system verification method and LSI manufacturing method using the system verification equipment
A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a...
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7039894 |
Method, system and program product for specifying and using dials having phased default values to configure a simulated or physical digital system
In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a...
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7035785 |
Mechanism for estimating and controlling di/dt-induced power supply voltage variations
A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the...
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7036097 |
Method for designing a cascade of digital filters for use in controling an electrolysis cell
A method for designing a cascade of digital filters for use in the control of an electrolytic reduction cell by specifying the frequency and time response characteristics of the transfer function...
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7036095 |
Clock generation system for a prototyping apparatus
A clock signal generation and distribution system for a prototyping apparatus of an electronic system comprises at least one clock signal generation and distribution subsystem for distributing at...
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7035781 |
Mixed language simulator
An HDL simulator having an automated interface to compiled or interpreted application code written in a general purpose language. The interface enables the HDL code to have a direct data access to...
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7036096 |
Estimating capacitances using information including feature sizes extracted from a netlist
The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool ( 120 ) to extract information associated with the inputs/outputs from a netlist. The...
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7036106 |
Automated processor generation system for designing a configurable processor and method for the same
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions...
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