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7299432 |
Method for preserving constraints during sequential reparameterization
A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs,...
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7299425 |
Method and apparatus to create bypass logic in a digital circuit design
A method and apparatus to create bypass logic in a digital circuit design comprising coupling a first latency delay unit to a data input of the conditional state element (e.g., a flip-flop)....
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7299426 |
System and method to improve chip yield, reliability and performance
Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias...
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7296248 |
Method and apparatus for compiling a parameterized cell
A method of generating a parameterized cell is disclosed herein. The method comprises performing a compiling interpretation on a structure layout. The compiling interpretation includes i)...
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7296252 |
Clustering techniques for faster and better placement of VLSI circuits
A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given...
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7296245 |
Combined e-beam and optical exposure semiconductor lithography
Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design...
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7290224 |
Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit
A method and tool that capture, create, and integrate a clock specification to achieve a correct-by-construction design flow of a semiconductor product from a partially manufactured semiconductor...
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7290228 |
Hardware accelerator with a single partition for latches and combinational logic
A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred...
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7287320 |
Method for programming a routing layout design through one via layer
A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality...
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7286975 |
Method for developing embedded code for system simulations and for use in a HMI
The present invention concerns a method and apparatus for integrating a CAD model of a product and an HMI simulation model of a product into a format suitable to be run in a virtual reality...
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7287235 |
Method of simplifying a circuit for equivalence checking
A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a...
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7286976 |
Emulation of circuits with in-circuit memory
Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the...
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7283942 |
High speed techniques for simulating circuits
The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called...
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7283943 |
Method of modeling circuit cells for powergrid analysis
Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node...
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7284216 |
System and method for verifying signal propagation delays of circuit traces of a PCB layout
A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer ( 1 ). The computer includes: a setting module ( 10 ) for setting a...
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7279987 |
Method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator
A method, apparatus and program storage device for modeling an analog PLL for use in a digital simulator are disclosed. A model of a phase locked loop to be simulated in a digital simulator...
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7280953 |
Noise countermeasure determination method and apparatus and storage medium
A noise countermeasure determination method includes the step of obtaining an analyzing circuit judgement result by judging acceptability of the analyzing circuit based on a comparison of features...
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7281231 |
Integrated circuit structure and a design method thereof
The present invention discloses an integrated circuit structure and a design method thereof, in which a circuit passageway is arranged at each circuit element terminal in circuit design stage. The...
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7278119 |
Battery-optimized system-on-a-chip and applications thereof
A battery-optimized system-on-a-chip includes multimedia module, a high-speed interface, a processing module, on-chip memory, and an on-chip DC-to-DC converter. The multimedia module operably...
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7278118 |
Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the...
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7278124 |
Design method for semiconductor integrated circuit suppressing power supply noise
An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the...
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7277835 |
Boundary representation per feature methods and systems
Computer implemented methods and systems for CAD data exchange, and in particular for creating boundary representations (“breps”) on a feature-by-feature basis are disclosed. According to an...
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7275222 |
Method, apparatus, and computer program product for enhancing a power distribution system in a ceramic integrated circuit package
A method, apparatus, and computer program product are disclosed for automatically enhancing a power distribution system (PDS) in a ceramic integrated circuit package. The package includes multiple...
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7275223 |
Facilitating high-level validation of integrated circuits in parallel with development of blocks in a hierarchical design approach
A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated circuit) are designed. In an...
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7272813 |
Transparent re-mapping of parallel computational units
An design architecture for an application specific integrated circuit (ASIC) is disclosed. The design architecture of the ASIC includes a pre-determined number of redundant computational units such...
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7272801 |
System and method for process-flexible MEMS design and simulation
A system-level design and simulation environment utilizing a process specification tool that is programmatically integrated with the system level design and simulation environment thereby enabling...
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7272805 |
System and method for converting a flat netlist into a hierarchical netlist
System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and...
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7272807 |
Determining equivalent waveforms for distorted waveforms
An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced...
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7272802 |
R-cells containing CDM clamps
A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an...
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7269810 |
Global equivalent circuit modeling system for substrate mounted circuit components incorporating substrate dependent characteristics
The present invention is a substrate dependent circuit modeling system for substrate-mounted components. The height and dielectric constant of a substrate have a significant impact on the frequency...
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7269809 |
Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits
Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate...
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7269811 |
Method of and apparatus for specifying clock domains in electronic circuit designs
A method of specifying clock domains in electronic circuit designs in a system level design tool is disclosed. The method generally comprises steps of providing a design having a plurality of...
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7269803 |
System and method for mapping logical components to physical locations in an integrated circuit design environment
A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A...
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7266789 |
Method and apparatus of optimizing the IO collar of a peripheral image
An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of...
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7266788 |
Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while...
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7266786 |
Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems
A method and apparatus of a configurable address mapping and protection architecture and hardware for on-chip systems have been described.
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7266790 |
Method and system for logic equivalence checking
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on...
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7266487 |
Matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs
This invention relates to matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs. A method to efficiently design and...
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7266787 |
Method for optimising transistor performance in integrated circuits
A method ( 300 ) for optimising transistor performance in semiconductor integrated circuits built from standard cells ( 12 ), or custom transistor level layout, is disclosed. An active area of NMOS...
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7263477 |
Method and apparatus for modeling devices having different geometries
The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions...
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7263672 |
Methods, systems, and data models for describing an electrical device
A method and system are described for creating a metadata text file corresponding to a geometry of a physical layout and/or a circuit layout of an electrical device. The layouts are defined in a...
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7260517 |
Synchronization of multiple simulation domains in an EDA simulation environment
A simulation environment includes a number of simulation domains. Particular simulation domains in a simulation environment are selectively activated and deactivated such that performance and...
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7260810 |
Method of extracting properties of back end of line (BEOL) chip architecture
A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each...
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7260797 |
Method and apparatus for estimating parasitic capacitance
One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the...
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7260806 |
Printed wiring board design aiding apparatus, printed wiring board design aiding method, and printed wiring board design aiding program
The present invention provides a printed wiring board design aiding apparatus, method, and program that can easily and inexpensively predict the displacement of a printed wiring board of...
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7257798 |
Method and system for designing a timing closure of an integrated circuit
Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the...
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7254799 |
Method for allocating resources in heterogeneous nanowire crossbars having defective nanowire junctions
Various embodiments of the present invention provide methods for allocating nanowire junctions in a nanowire crossbar having one or more randomly distributed non-functional crossbar nanowire...
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7254790 |
Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops
A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into...
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7251791 |
Methods to generate state space models by closed forms and transfer functions by recursive algorithms for RLC interconnect and transmission line and their model reduction and simulations
There is provided a set of methods with the exact accuracy to effectively calculate the 2n-th order state space models of RLC distributed interconnect and transmission line in closed forms in time...
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7251795 |
Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design
A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal...
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