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7243269 |
Electronic device
There is provided an electronic device capable of device testing by using inexpensive testing devices. The electronic device is comprised of a receiver for receiving signals from a shield line and...
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7213185 |
Built-in self test circuit for integrated circuits
A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a...
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7203872 |
Cache based physical layer self test
A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The...
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7178078 |
Testing apparatus and testing method for an integrated circuit, and integrated circuit
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a...
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7177965 |
Linking addressable shadow port and protocol for serial bus networks
Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or...
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7168054 |
Software traffic generator/analyzer
A computer program product that runs via a processor system for generating and/or analyzing traffic signals for testing at least parts of integrated-circuit-environments designed to handle traffic...
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7155370 |
Reusable, built-in self-test methodology for computer systems
A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit...
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7139957 |
Automatic self test of an integrated circuit component via AC I/O loopback
A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically...
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7076711 |
Automatic testing of microprocessor bus integrity
Integrated circuit bus integrity may be verified without specialized test equipment. In a diagnostic mode, the integrated circuit may output a series of predetermined activation patterns onto the...
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7047458 |
Testing methodology and apparatus for interconnects
A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a...
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7047444 |
Address selection for testing of a microprocessor
A microprocessor with built-in test, comprising: a register for retaining a test address of a test program; a next address generation logic for generating a command address of a command scheduled...
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6934205 |
Bist for parallel testing of on chip memory
A processor assisted memory BIST to identify detective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is...
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6901546 |
Enhanced debug scheme for LBIST
A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking...
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6886124 |
Low hardware overhead scan based 3-weight weighted random BIST architectures
Techniques for generating a test set for hard to detect faults is disclosed. A set of hard to detect faults is identified. A test set for the hard to detect faults is generated by using an improved...
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6874108 |
Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
A method of fault tolerant operation of an adaptive computing system includes identifying a faulty resource in a signal path of the adaptive computing system, reconfiguring the signal path to avoid...
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6826100 |
Push button mode automatic pattern switching for interconnect built-in self test
A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test...
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6825688 |
System for yield enhancement in programmable logic
A system is provided for yield enhancement in programmable logic. The system includes first and second random combinational logic, first and second sets of IP logic blocks, and first and second...
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6819114 |
Monitor having a self testing circuit
A monitor includes a display panel, a displaying circuit, a connector and a self testing circuit. The self testing circuit has a testing signal generator, a switch circuit and a detecting circuit....
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6754849 |
Method of and apparatus for testing CPU built-in RAM mixed LSI
A test apparatus includes a switch switched towards the ROM under the control of a signal output from the tester. When the switch is switched towards the ROM, the computer program for carrying out...
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6732311 |
On-chip debugger
An integrated circuit debugger incorporated into an integrated circuit, allowing direct access to internal points within the integrated circuit. By having direct access to internal points within...
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6728916 |
Hierarchical built-in self-test for system-on-chip design
Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete...
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6721905 |
Processor
The present invention provides a processor including a self-diagnostic function. The processor comprises: an arithmetic circuit including an adder-subtracter, which is a diagnostic object; a data...
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6704895 |
Integrated circuit with emulation register in JTAG JAP
An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path...
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6704892 |
Automated clock alignment for testing processors in a bypass mode
In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock...
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6704889 |
Enhanced embedded logic analyzer
Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and...
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6671838 |
Method and apparatus for programmable LBIST channel weighting
An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a...
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6662314 |
Microcomputer including program for rewriting data in an internal flash memory
A microcomputer of the present invention permits a direct control of a rewrite operation on an internal flash-memory to enhance the efficiency of a debugging operation. The microcomputer has a...
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6643796 |
Method and apparatus for providing cooperative fault recovery between a processor and a service processor
A method and apparatus for providing cooperative fault recovery between an operating system and a service processor allows fault detection and recovery capability utilizing a service processor...
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6641045 |
Portable electronic device with self-diagnostic function
A portable data processing device is disclosed which, when connected to and activated by an external device, transmits initial response data to the external device, performs a self-diagnosis of...
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6618634 |
Microcomputer system using repeated reset to enter different operating modes and method to do the same
A microcomputer system and method of utilizing a repeated reset operation to enter the microcomputer system into different operating modes, particularly a microcomputer system without a keyboard,...
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6581019 |
Computer-system-on-a-chip with test-mode addressing of normally off-bus input/output ports
An embedded-controller-based system, such as a personal digital assistant (PDA), includes a system-on-a-chip with a processor, system bus, memory, and system-bus peripherals. The system-bus...
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6570407 |
Scannable latch for a dynamic circuit
A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test...
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6567944 |
Boundary scan cell design for high performance I/O cells
A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the...
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6564348 |
Method and apparatus for storing and using chipset built-in self-test signatures
A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data...
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6557157 |
Method for designing complex digital and integrated circuits as well as a circuit structure
The data flows of a system are allocated an arithmetic or logical function per function block (ALU-block), forming a RAM control. The ALU-blocks are specialized according to individual processing...
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6550031 |
Transparently gathering a chips multiple internal states via scan path and a trigger
A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as...
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6546505 |
Processor condition sensing circuits, systems and methods
A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.
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6539497 |
IC with selectively applied functional and test clocks
A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further...
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6539338 |
Self-diagnostic testing of a network interface adapter
A method and apparatus for implementing a self-diagnostic capability in a network interface adapter in which failure data is provided to a host processor. The host processor may report the failure...
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6502190 |
System and method for computer system initialization to maximize fault isolation using JTAG
A sequenced initialization used for maximizing detection of errors and failures and triggering of respective attention signals. A number of computer devices each having a JTAG interface, an...
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6484273 |
Integrated EJTAG external bus interface
An apparatus comprising a processor and an interface. The processor may be configured to support system-on-chip debugging. The interface circuit may be coupled to the processor and configured to...
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6438722 |
Method and system for testing an integrated circuit
The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular...
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6427160 |
Method and system for testing floating point logic
In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and...
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6425102 |
Digital signal processor with halt state checking during self-test
The objective of the invention is to provide a DSP that can perform hold testing, which evaluates the halt state of the DSP core, during DSP core self-testing. DSP circuit 2 has input scheduler 8...
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6421773 |
Sequence control circuit
A sequence control circuit provided in such as a test pattern generator of a memory test apparatus, and made capable of designating a plurality of branches according to a plurality of branch...
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6311311 |
Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test
A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate...
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6304983 |
Checkpoint logging without checkpoint display device availability
A processor register is reserved by early firmware code to be employed for checkpoint logging or for storing diagnostic information at the time of failure before a checkpoint display device,...
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6223312 |
Test-facilitating circuit for information processing devices
A test-facilitating circuit selectively carries out tests for self-testing and for fault diagnosis and failure analysis. In a test for fault diagnosis or failure analysis, necessary test data are...
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6067649 |
Method and apparatus for a low power self test of a memory subsystem
A technique self tests a memory system having memory modules that operate at a normal operating clock rate during a normal operating mode. Each memory module has multiple arrays of synchronous...
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6052806 |
Method and apparatus for testing an integrated circuit device
An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral...
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