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7624335 |
Verifying a file in a system with duplicate segment elimination using segmention-independent checksums
Verifying a file in a system with duplicate segment elimination is disclosed. A data file is segmented into a plurality of distinct data segments, and a checksum is computed for each of the...
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7607036 |
System and method for enabling continued use of trim values within an implantable medical device following a parity error
Techniques are described for use by an implantable medical device equipped to use trim values, which allow the device to continue to use trim values despite certain memory errors such as parity...
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7603614 |
Method and system for indicating an executable as trojan horse
A method and system for indicating an executable as Trojan Horse, based on the CRC values of the routines of an executable. The method comprising a preliminary stage in which the CRC values of the...
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7596739 |
Method and system for data replication
A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n−1) of physical blocks required to...
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7594051 |
Storage apparatus
The storage apparatus is provided with a host interface adapter unit, a storage interface adapter unit, a cache memory unit storing data temporarily, a switch unit connecting the host interface...
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7581163 |
Detection of corrupted memory pointers within a packet-processing device
Techniques are described for detecting corruption of buffer pointers passed between a local processor and a remote processor on a network device. For example, the first processor, which may be a...
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7577207 |
Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density...
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7559009 |
System and method for performing parity checks in disk storage systems
A cyclic redundancy check (CRC) system for a storage controller comprises a memory that stores first sector data and a corresponding CRC non-zero seed value. A buffer control module includes a CRC...
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7523342 |
Data and control integrity for transactions in a computer system
A computer system configured to enhance data protection. A computer system includes one or more clients, such as processing subsystems and a memory subsystem interconnected via a network....
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7496824 |
Data recording device and method, data reproduction device and method, information recording medium, program-containing medium, and program
A data-recording/reproducing apparatus and method, that determine a reproduction position with high degree of reliability for data recorded on an information-recording medium even after the data is...
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7472332 |
Method for the reliability of host data stored on fibre channel attached storage subsystems
A method for improving the reliability of host data stored on Fiber Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated,...
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7453960 |
LDPC encoder and encoder and method thereof
A decoder for decoding low-density parity-check codes comprises a first calculator to calculate LLrR ml , for each parity check equation, at iteration i−1. A detector detects LLrR ml , at...
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7451387 |
Autonomous method and apparatus for mitigating soft-errors in integrated circuit memory storage devices at run-time
Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon...
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7428693 |
Error-detecting encoding and decoding apparatus and dividing apparatus
Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string,...
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7415633 |
Method and apparatus for preventing and recovering from TLB corruption by soft error
A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a...
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7395462 |
Defect estimation apparatus and related method
A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for...
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7380200 |
Soft error detection and correction by 2-dimensional parity
The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used...
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7370138 |
Mobile communication terminal including NAND flash memory and method for booting the same
A mobile communication terminal with a NAND flash memory is described. The terminal includes a memory for storing address information indicative of a start address of a specific area including boot...
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7350137 |
Method and circuit for error correction in CAM cells
A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for...
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7350132 |
Nanoscale interconnection interface
One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The...
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7337352 |
Cache entry error-connecting code (ECC) based at least on cache entry data and memory address
Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A...
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7328305 |
Dynamic parity distribution technique
A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file...
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7278090 |
Correction parameter determination system
An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop...
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7266759 |
Semiconductor integrated circuit device and error checking and correcting method thereof
A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data...
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7263646 |
Method and apparatus for skew compensation
A method that measures a skew between a data signal and a clock signal at a receiving end of a serial link and then adjusts a phase relationship between the data signal and the clock signal to...
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7251773 |
Beacon to visually locate memory module
One embodiment disclosed relates to a method of visually locating a memory module. An electronic communication is received by circuitry on the memory module to be visually located. A beacon state...
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7243290 |
Data encoding for fast CAM and TCAM access times
A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an...
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7240277 |
Memory error detection reporting
A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection...
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7231582 |
Method and system to encode and decode wide data words
A parity generation circuit includes a plurality of bit-generation circuits. Each bit-generation circuit receives respective data bits and a respective hard latch signal, and operates to generate a...
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7191380 |
Defect-tolerant and fault-tolerant circuit interconnections
Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different,...
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7191378 |
Method and system for providing low density parity check (LDPC) encoding
An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity...
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7188270 |
Method and system for a disk fault tolerance in a disk array using rotating parity
A two-dimensional parity method and system for rotating parity information in a disk array, such as a RAID, to provide multiple disk fault tolerance with reduced write bottlenecks, is presented....
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7111228 |
System and method for performing parity checks in disk storage system
A system for maintaining cyclic redundancy check (“CRC”) protection of XOR'ed data sectors includes a register that is initialized with a non-zero seed value used for generating sector CRC...
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7103826 |
Memory system and controller for same
The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information...
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7093190 |
System and method for handling parity errors in a data processing system
A method and apparatus is provided for handling parity errors within a data processing system. Each occurrence of a parity error is attributed to an addressable memory location or a block of memory...
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7076607 |
System, method, and apparatus for storing segmented data and corresponding parity data
A system, method, and apparatus are disclosed for storing segmented data and corresponding parity data with modules configured to functionally execute the necessary steps of storing segmented data...
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7010740 |
Data storage system having no-operation command
A system wherein data is read from, and store in, a memory, such data having associated therewith an address/control portion. The system includes a pair of controller sections, one of such sections...
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6971041 |
Cache entry error-correcting code (ECC) based at least on cache entry data and memory address
Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A...
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6961892 |
Address information detecting apparatus and address information detecting method
An address information detecting apparatus in accordance with the present invention is arranged such that a first interpolation address generating section generates a first interpolation address...
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6961877 |
System and method for in-line error correction for storage systems
The present invention provides a method and system for performing in-line error correction in a disk storage system. The system includes an error correction (ECC) module; and a first memory storage...
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6941493 |
Memory subsystem including an error detection mechanism for address and control signals
A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests...
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6938201 |
Error detection system for a FIFO memory
An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data...
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6912686 |
Apparatus and methods for detecting errors in data
Mechanisms and techniques allow a data storage system to detect errors in data received for storage within the data storage system. To do so, the data storage system receives, from an originator...
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6904556 |
Systems and methods which utilize parity sets
A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory...
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6842902 |
Robust device driver token management for upgraded computers using legacy device cards
In one aspect of the invention is a method for robust device token management. In x+ bit computers using x bit device cards, tokens are used for managing communication requests from applications to...
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6807649 |
Encryption keys for multiple drive fault tolerance
A system and related method for calculating parity information for disk array drive failure recovery. More specifically, using eight bit coefficients and calculating parity information using valid...
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6807642 |
Cluster system having virtual raid, computer for the cluster system, and parity calculation method in the cluster system
A cluster system managing a plurality of disk drives as a component of a virtual RAID comprises a cluster manager and a control unit. The cluster manager converts a global command G into local...
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6804799 |
Using type bits to track storage of ECC and predecode bits in a level two cache
A microprocessor configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit, and instruction cache, a data cache, and a...
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6801625 |
Apparatus and method for stripping parity bits from an input stream
The disclosed parity stripping technique quickly and efficiently converts a multi-byte input stream having parity bits to an output data stream that contains the same data as the input stream but...
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6745366 |
Error correcting method and apparatus for N:N&plus 1 channel codes
A method for correcting an error in N:N+1 channel codes categorizes 2 N+1 codeword (N+1)-tuples into M subsets of codeword (N+1)-tuples, wherein each subset G has N G codeword (N+1)-tuples and...
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