Matches 201 - 250 out of 396 < 1 2 3 4 5 6 7 8 >
Match Document Document Title
5177747 Personal computer memory bank parity error indicator  
A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate...
5173905 Parity and error correction coding on integrated circuit addresses  
A more secure method for selecting and addressing individual integrated circuit chips and memory locations, registers or input/output ports within the chips includes supplying the chips with...
5151906 Semiconductor memory device having self-correcting function  
A semiconductor memory device having a self-correcting function comprises memory cells for storing data and memory cells for storing parity bit data. The criterion of detecting in the first read...
5142541 Error-bit generating circuit for use in a non-volatile semiconductor memory device  
An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational...
5140597 Semiconductor memory device having mask ROM structure  
A semiconductor memory device is provided with a memory cell array having a plurality of memory cells formed by a mask ROM. The memory cell array has a data area in which stored data of n bits is...
5130992 File-based redundant parity protection in a parallel computing system  
This is method for parity protecting distributed data files in a multi-node, parallel data processing network, with each node having a data store. Each data file is organized as a series of fixed...
5123019 Method for processing binary code words  
In a method for processing incoming code words that are accompanied by parity bits and that, in the course of being transmitted, undergo a digital attenuation and/or a code conversion for...
5111458 Hardware arrangement for storing error information in pipelined data processing system and method therefor  
In order to simplify a hardware arrangement for obtaining error information in a pipelined data processing system which includes serially coupled stages, two separate (first and second) error...
5095485 Microprocessor equipped with parity control unit on same chip  
A microprocessor having a on-chip redundant control unit is disclosed. This processor includes a set of data terminals, an execution unit and a data bus buffer coupled between the set of data...
5088092 Width-expansible memory integrity structure  
A width-expansible ROM/PROM memory structure includes a plurality of duplicate-type ROM/PROM data memory chips and includes a duplicate-type ROM/PROM parity memory chip. Stored data words of "n"...
5079747 Semiconductor memory device having diagnostic unit operable on parallel data bits  
A semiconductor memory device is installed in one of a single data output and a parallel data output model, and a single data output unit associated with a first diagnostic unit and a parallel data...
5077744 Method for error protection in telephone switching installations  
Data are error protected; dual memory control is utilized. From one memory control only write-in data are transmitted in addition to address and control signals; from the other memory control only...
5077720 Optical information recording and reproducing system and optical disk  
A read only optical disk is provided which includes (1) information sectors having recorded therein first encoded data obtained by encoding data by a first error detection/correction code to...
5072450 Method and apparatus for error detection and localization  
A computer system reads data from selected locations in a memory while each address applied to the memory is temporarily stored in a register. If a data error is detected, two flipflops are set,...
5052002 Method of detecting and indicating errors in a memory device  
An EEPROM system with an error detecting function includes: a memory cell matrix composed of a plurality of MOS memory cells and a plurality of bit lines connected separately to the plurality of...
5052001 Multiple memory bank parity checking system  
A ROM/PROM memory system circuit structure provides for vertical expansion of data words while providing for enablement of parity checking by the addition of a single auxiliary ROM/PROM memory chip...
5043943 Cache memory with a parity write control circuit  
A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE x ) signals to enable a write amplifier to individually...
5023876 Method and apparatus for detecting finally recorded sector  
In a finally recorded sector detecting system suitable for a write-once type optical disc device, an error correction code or error detection code provided for each index sector is utilized to...
5022030 Skewed XOR data storage process  
A method and apparatus for writing and reading multiplexed data in a plurality of data storage systems, including skewed XOR data for improving data retrieval integrity with minimal write time.
5003542 Semiconductor memory device having error correcting circuit and method for correcting error  
In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through...
4967415 EEPROM system with bit error detecting function  
An EEPROM system with an error detecting function includes: a memory cell matrix composed of a plurality of MOS memory cells and a plurality of bit lines connected separately to the plurality of...
4965802 Memory arrangement utilized for IC card  
An information recording medium includes a memory section for storing therein information inputted from an external apparatus, information generated internally on the basis of the inputted...
4962501 Bus data transmission verification system  
A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each...
4959835 Semiconductor memory  
A memory management unit is capable of judging that a specific bit has been partially rewritten by checking it against a dummy bit stored in a tag memory which is included in the memory management...
4942579 High-speed, high-capacity, fault-tolerant error-correcting storage system  
A storage system for dynamic and trasparent error correction has a number of first individual storage devices for information and a second individual storage device for error code bits that are...
4928281 Semiconductor memory  
A semiconductor memory includes a memory array which outputs storage data, at least one data unit at a time, each data unit having a plurality of bits including a parity bit, a parity check circuit...
4920536 Error recovery scheme for destaging cache data in a multi-memory system  
In a data processing system in which a processor has a cache receiving data staged from at least two main memories. Performance is enhanced by providing an indicator identifying the main memory...
4918695 Failure detection for partial write operations for memories  
A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any...
4918693 Apparatus for physically locating faulty electrical components  
In a computer system in which addressable components are physically organized on separately-replaceable printed circuit boards each containing an array of separately addressable components,...
4916703 Handling errors in the C bit of a storage key  
A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the...
4903219 Method of identifying flag bits  
A technique for determining and resetting one or more flags in a digital word in memory in which the flags comprise added bits in known locations different from any of the magnitude bits in the...
4884270 Easily cascadable and testable cache memory  
The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read...
4860262 Cache memory reset responsive to change in main memory  
A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are...
4860293 Supervision circuit for a non-encoded binary bit stream  
An error supervision circuit for a non-encoded binary bit stream running through an elastic store comprising a memory having n locations, the bit rate of the stream supplied to the input of the...
4849978 Memory unit backup using checksum  
A memory system backup for use in a tightly or loosely coupled multiprocessor system. A plurality of primary memory units having substantially the same configuration are backed up by a single...
4837743 Architecture for memory multiplexing  
A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory...
4837767 Bus adapter module with improved error recovery in a multibus computer system  
A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal...
4833655 FIFO memory with decreased fall-through delay  
A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled...
4811347 Apparatus and method for monitoring memory accesses and detecting memory errors  
A data processing arrangement which comprises a memory device provided with a memory with a first field in which memory words are stored or can be stored and a second field in which an error...
4809279 Enhanced parity detection for wide ROM/PROM memory structure  
A wide ROM-PROM memory is structured of multiple memory chips in parallel plus an auxiliary parity memory chip to hold parity bits for each corresponding addressable location in each memory chip....
4809278 Specialized parity detection system for wide memory structure  
A parity detection scheme for a wide memory structure of RAM memory chips provides an auxiliary RAM parity memory chip to store parity data for each corresponding input line of each memory chip...
4800535 Interleaved memory addressing system and method using a parity signal  
A high performance interleaved memory addressing system and method. A plurality of banks of random access memory devices are provided. The appropriate bank for a given memory address is selected...
4799222 Address transform method and apparatus for transferring addresses  
An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are...
4785452 Error detection using variable field parity checking  
A variable number of parity bits or error correction code per word is used to increase error detection for words having the extra parity bits in a control store. Since some words do not utilize all...
4774712 Redundant storage device having address determined by parity of lower address bits  
A memory device for storing data and providing address and data line error detection is disclosed. A memory holds two copies of data, each copy of data having opposite parity dependent on its...
4768193 Semiconductor memory device having error correction function and incorporating redundancy configuration  
A semiconductor memory device having a main memory cell array including a plurality of rows of cell arrays, each row corresponds to a two-dimensional virtual matrix configuration. A redundancy...
4761785 Parity spreading to enhance storage access  
A storage management mechanism distributes parity blocks corresponding to multiple data blocks substantially equally among a set of storage devices. N storage units in a set are divided into a...
4761783 Apparatus and method for reporting occurrences of errors in signals stored in a data processor  
The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals;...
4757440 Pipelined data stack with access through-checking  
A virtual stack structure utilizing Write Pointers and Read Pointers for providing pipelined data words on a first-in first-out basis to a memory structure is described. The virtual stack structure...
4706250 Method and apparatus for correcting multibyte errors having improved two-level code structure  
A system for correcting errors in data read from a direct access storage device employs an extendable, two-level coding scheme having n subblocks in a relatively long variable-length block of data,...
Matches 201 - 250 out of 396 < 1 2 3 4 5 6 7 8 >