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5611072 Cache with an extended single cycle read/write system and method  
A method for updating a LRU array in a cache having a RAM. The LRU array has a self-timing signal for the read operation of the LRU array, in conjunction with a cache RAM read cycle. According to...
5594741 Method for control of random test vector generation  
A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the...
5592499 Semiconductor memory device  
A semiconductor memory device includes a memory cell array for storing information and parity bits, a register circuit for temporarily holding the information and parity bits in respective bit...
5588012 Apparatus and method for ensuring data in external storage system  
In an apparatus and method for ensuring data in an external storage system, the system includes an external storage controller for transferring read data from at least one external storage device,...
5586129 Parity bit memory simulator  
A parity bit memory simulator including a parity bit memory formed of a single bit memory of fixed address length, which replaces the single bit parity RAM of variable address length of...
5583876 Disk array device and method of updating error correction codes by collectively writing new error correction code at sequentially accessible locations  
When new data for writing is sent from a host device, old data and old parities are read after a search time respectively, and a new parity is generated with the new data, the old data and the old...
5577055 Method and circuit device to control a memory  
A method and a circuit device control insertion and storage of digital information in a memory and retrieval of the information from the memory. The method and circuit device ensure the digital...
5574736 Data storage device and method of operation  
An improved storage device, such as a disk drive, for use in an array of drives. Each drive has logic and Exclusive Or calculation means. Data to be written is sent to the target disk drive from...
5566194 Method and apparatus to improve read reliability in semiconductor memories  
Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error...
5561672 Apparatus for preventing computer data destructively read out from storage unit  
A data transfer control system for a computer for preventing destructive read out of data from an external storage unit during a data transfer operation to a storage unit of the computer. The...
5546409 Error correction encoding and decoding system  
In an error correction encoding system, information codes in the form of a data matrix having row addresses and column addresses are stored in memory. A first error correction encoder extracts the...
5544341 Data access apparatus for preventing further cache access in case of an error during block data transfer  
A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a...
5530948 System and method for command queuing on raid levels 4 and 5 parity drives  
The queuing of commands on an input/output controller for a parity drive, in a level 4 or level 5 redundant array of inexpensive disk drives responds to receipt of a write instruction with appended...
5522065 Method for performing write operations in a parity fault tolerant disk array  
A method for managing disk operations for a computer having a disk array utilizing parity fault tolerant and recovery techniques. A disk READ request results in a copy of the data and its...
5522032 Raid level 5 with free blocks parity cache  
A system for writing data to a disk array includes a cache memory coupled to the disk array for storing data indicative of locations on the disk array and parity blocks associated with parity...
5515381 Sequential parity correction for error-correcting RAM array  
An apparatus and method of correcting parity errors in a fault tolerant computer system. Data and associated parity are checked in parallel with use of the data by an ALU. Upon detection of an...
5502728 Large, fault-tolerant, non-volatile, multiported memory  
A large, fault tolerant, highly reliable semiconductor data storage system (memory) is designed to have the memory function striped across multiple symbol planes which comprise individual fault...
5479641 Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking  
A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array,...
5477553 Compressed memory address parity checking apparatus and method  
A compressed memory address parity (CMAP) checking apparatus for checking the parity of data read from a data memory comprising a low capacity auxiliary memory with 2 N address spaces and an...
5469453 Data corrections applicable to redundant arrays of independent disks  
Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as...
5453999 Address verification system using parity for transmitting and receiving circuits  
An address verification system for providing address error detection whether the error originates at the address generation circuitry, the address transmission path, or the address receiving...
5453998 Circuit for processing data to/from an array of disks  
An array processing circuit which operates on a M row-N column array of digital words includes a first set of N memories, each of which asynchronously receives a respective column of words from a...
5450565 Circuit and method for selecting a set in a set associative cache  
A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive...
5438575 Data storage system with stale data detector and method of operation  
A low cost, high speed data storage system provides word-by-word stale data detection while avoiding the need to both read and write a single memory location during a memory read operation. Two...
5434871 Continuous embedded parity checking for error detection in memory structures  
A method of and apparatus for continuous parity checking within a CMOS SRAM memory system. Each cell has added circuitry which permits continuous reading of the binary state of the cell. The states...
5428632 Control circuit for dual port memory  
A memory device provides a control circuit attached to a parity bit position of a memory array. When a selected single bit within an array entry has its value changed without affecting the...
5412661 Two-dimensional disk array  
A data storage system architecture having an array of small data storage disks, organized into logical rows and columns, with each disk coupled to two disk controllers via two independent...
5412671 Data protection and error correction, particularly for general register sets  
A data protection and correction scheme is implemented by providing main and shadow stores for groups of data bits from a segmented data word. The data bits are divided into even and odd address...
5404495 Microcomputer having an error-correcting function based on a detected parity error  
A microcomputer having an error correction function includes a summing function for calculating a total-sum of data associated with a block of stored data, a total-sum changing function for...
5392302 Address error detection technique for increasing the reliability of a storage subsystem  
A fault detection arrangement provides error detection and verification of generated address sequences for the execution of read/write operations in a storage subsystem. The arrangement also...
5390313 Data storage system with data mirroring and reduced access time data retrieval  
A data storage system with data mirroring and reduced access time data retrieval includes at least one pair of rotating data storage media each having a plurality of generally identical data...
5367526 Memory module, parity bit emulator, and associated method for parity bit emulation  
A memory module, parity bit emulator, and method which emulate storing and retrieving a parity bit from memory. The memory module includes a memory for storing a data word which is retrieved from...
5355377 Auto-selectable self-parity generator  
A parity generating circuit that can replace the parity bit DRAM on a 9-bit SIMM. The parity generating circuit includes a parity generating tree which outputs the resulting even parity from the 8...
5345582 Failure detection for instruction processor associative cache memories  
A system for detecting failures in a cache memory stores data words that may represent instructions or operands in plurality of blocks. The data words are divided into a plurality of data bit...
5339322 Cache tag parity detect circuit  
A memory which is cleared by simultaneously clearing a special bit in each entry within the memory, an extra bit, used for other purposes, is also cleared. When both bits have a value of 0, parity...
5337317 Minimizing the programming time in a semiconductor integrated memory circuit having an error correction function  
A semiconductor integrated memory circuit includes therein a PROM having a plurality of bit cell groups, each of which includes a set of data bit cells for storing data and a set of check bit cells...
5337322 Method of processing stored data containing parity data  
A method for efficiently storing data into a data storage system containing parity data comprises the steps of: determining the data storage units and the portions of each data storage unit where...
5333305 Method for improving partial stripe write performance in disk array subsystems  
A method and apparatus for improving disk performance during partial stripe write operations in a computer system having a disk array subsystem utilizing parity fault tolerance technique. When a...
5325375 Method and apparatus for non-atomic level parity protection for storing data in a random access memory  
The method and apparatus provides a parity bit for every m multiples of b bits, a group of b bits being the smallest number of bits that can be manipulated by the CPU. The parity bit is computed...
5321706 Method and apparatus for checking the address and contents of a memory array  
A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a...
5313475 ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme  
An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers...
5305326 High availability disk arrays  
A method for handling data in a plurality of data storage disks having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a degraded mode...
5285456 System and method for improving the integrity of control information  
A system and method for verifying the integrity of control information and informational data. One embodiment of the present invention verifies the integrity of control information received from a...
5257362 Method and means for ensuring single pass small read/write access to variable length records stored on selected DASDs in a DASD array  
Write update of variable length records stored in row major order on an array of N DASDs is facilitated by utilizing the correlation between byte offsets of a variable length record and the byte...
5233618 Data correcting applicable to redundant arrays of independent disks  
Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as...
5226043 Apparatus and method for data error detection and correction and address error detection in a memory system  
An error detection and correction apparatus and method in a memory system for performing single symbol error correction and at least double symbol error detection of data errors and single symbol...
5224107 Method in a parallel test apparatus for semiconductor memories  
A method in a parallel test apparatus provides for parallel testing a plurality of memory cells of a semiconductor module in parallel. The information read from the memory cells that are forwarded...
5216656 Method for recording a CD-RAM which is compatible with a conventional CD recording format while allowing fast accessing  
A method of recording user data on a DC-RAM disc medium comprising the steps of recording servo signals in a pair of spaced apart servo areas in each one of a predetermined number of segments which...
5206866 Bit error correcting circuit for a nonvolatile memory  
A bit correction circuit for a nonvolatile memory is connected between a non-volatile memory and a control circuit such as a microcomputer. The nonvolatile memory has a plurality of sets of memory...
5195096 Method of functionally testing cache tag RAMs in limited-access processor systems  
A method of functionally testing cache tag RAMs in processor systems where the kernel is typically inaccessible. A test program first determines whether a fault exists at all within the cache tag...
Matches 151 - 200 out of 396 < 1 2 3 4 5 6 7 8 >