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7617442 Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices  
Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be...
7607068 Apparatus and method for generating a Galois-field syndrome  
The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first...
7600180 Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals  
Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when...
7600173 Retransmission control method and communications device  
A retransmission control method comprising: generating N parity check matrices; generating a generator matrix containing a check symbol generator matrix contained in the first parity check matrix;...
7584400 Clash-free irregular-repeat-accumulate code  
Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix...
7577896 Apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUS)  
The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC...
7552378 Semiconductor device improving error correction processing rate  
In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the...
7543213 Turbo decoder and dynamic decoding method used for same  
To provide a turbo decoding method capable of significantly improving efficiency of a determination as to whether or not to end decoding. If the decoding by a turbo decoder is started, a soft...
7532132 Systematic encoding and decoding of chain reaction codes  
A method of encoding data into a chain reaction code includes generating a set of input symbols from input data. Subsequently, one or more non-systematic output symbols is generated from the set of...
7530003 Permuting MTR code with ECC without need for second MTR code  
Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint. In one embodiment, a...
7519898 Iterative decoding of linear block codes by adapting the parity check matrix  
A method of decoding linear block code uses an iterative message passing algorithm with a binary image of a parity check matrix of the linear block code, wherein the parity check matrix is adapted...
7516388 LDPC code inspection matrix generation method  
A method of generating check matrixes for LDPC codes includes analyzing a “Sum-Product Algorithm” for Low-Density Parity-Check codes, on the assumption that a Log Likelihood Ratio between...
7509559 Apparatus and method for parity generation in a data-packing device  
A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the...
7509557 De-interleaver, mobile communication terminal, and de-interleaving method  
A de-interleaver has a TTI frame buffer storing a TTI frame before de-interleaving, a P bit information table storing P bit information containing the size and added position of P bits to be added...
RE40684 Fast cyclic redundancy check (CRC) generation  
A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is...
7493548 Method and apparatus for encoding and decoding data  
A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix H b and wherein H b comprises a section H b1 and a section H b2 , and wherein H b2 comprises a first...
7484168 Parity check outer code and runlength constrained outer code usable with parity bits  
The invention provides a channel coding method for encoding systematic data for transmission in a communication channel. The systematic data has a runlength constraint. In the method, data words...
7484167 Error detection using codes targeted to prescribed error types  
Techniques are described for detecting error events in codewords detected from data signals transmitted via a communication system. The error events are detected with an error detection code that...
7484158 Method for decoding a low-density parity check (LDPC) codeword  
A method for decoding a noisy codeword (y) received from a communication channel as the result of a LDPC codeword (b) having a number (N) of codeword bits is disclosed. Each codeword bit consists...
7453960 LDPC encoder and encoder and method thereof  
A decoder for decoding low-density parity-check codes comprises a first calculator to calculate LLrR ml , for each parity check equation, at iteration i−1. A detector detects LLrR ml , at...
7447985 Efficient design to implement min**/min**- or max**/max**- functions in LDPC (low density parity check) decoders  
Efficient design to implement min**/min**− or max**/max**− functions in LDPC (Low Density Parity Check) decoders. When compared to prior art approaches, the novel and efficient implementation...
7437658 Disk array device, parity data generating circuit for RAID and Galois field multiplying circuit  
In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table...
7426683 Semiconductor memory device equipped with error correction circuit  
The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors...
7415658 Forward error correction mapping and de-mapping techniques  
Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.
7406654 Coding circuit for recording data on DVD disk  
A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a buffer manager which successively reads the digital data m bytes at a time...
7406648 Methods for coding and decoding LDPC codes, and method for forming LDPC parity check matrix  
Provided are methods for encoding and decoding low-density parity-check (LDPC) codes and a method for forming an LDPC parity check matrix. The method for forming the LDPC parity check matrix,...
7395494 Apparatus for encoding and decoding of low-density parity-check codes, and method thereof  
An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row...
7395487 Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder  
Common circuitry supporting both bit node and check node processing in LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a decoder may use the same circuitry to...
7386780 Method and apparatus for encoding and precoding digital data within modulation code constraints  
Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not...
7386627 Methods and apparatus for precomputing checksums for streaming media  
A method for storing streaming media data packets in a cache includes receiving a first streaming media data packet from a streaming media server, the first streaming media data packet comprising...
7383492 First-in/first-out (FIFO) information protection and error detection method and apparatus  
A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the...
7366971 Semiconductor memory having sub-party cell array error correction  
Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit...
7350130 Decoding LDPC (low density parity check) code with new operators based on min* operator  
Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value...
7340672 Providing data integrity for data streams  
Provided are a method, system, and article of manufacture for providing data integrity for data streams. Input data streams are received. A parity data stream is generated by computing parity data...
7340003 Multi-mode iterative detector  
A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a...
7328397 Method for performing error corrections of digital information codified as a symbol sequence  
A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to...
7328305 Dynamic parity distribution technique  
A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file...
7315970 Semiconductor device to improve data retention characteristics of DRAM  
A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and...
7296216 Stopping and/or reducing oscillations in low density parity check (LDPC) decoding  
Stopping or reducing oscillations in Low Density Parity Check (LDPC) codes. A novel solution is presented that completely eliminates and/or substantially reduces the oscillations that are...
7287213 Method and system to provide modular parallel precoding in optical duobinary transmission systems  
A circuit using modular based parallel processing calculates the cumulative parity of a binary number input sequence. The circuit is used, for example, to implement a precoder for an optical...
7283528 On the fly header checksum processing using dedicated logic  
A packet header processing engine includes a packet processing unit that is configured to generate the packet header information based on the packet header data. A checksum generating unit is...
7280468 Apparatus for constant amplitude coded bi-orthogonal demodulation  
A constant amplitude coded bi-orthogonal demodulator demodulates the received constant amplitude bi-orthogonal modulated data, cancels the parity bits to generate the serial data, detects the...
7278085 Simple error-correction codes for data buffers  
A method of and apparatus for handling errors occurring in data stored in memory is presented. Data to be stored in a buffer memory is applied to a generator matrix to generate parity check bits....
7249307 Flexible rate and punctured zigzag codes  
A generalized zigzag code is described where the code segments (each including one parity bit and information bits) of a block are not necessarily of uniform length. For coding rates in which the...
7246304 Decoding architecture for low density parity check codes  
Architectures for decoding low density parity check codes permit varying degrees of hardware sharing to balance throughput, power consumption and area requirements. The LDPC decoding architectures...
7237174 Method and system for providing short block length low density parity check (LDPC) codes in support of broadband satellite applications  
An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is...
7234098 Method and apparatus for providing reduced memory low density parity check (LDPC) codes  
An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the...
7231582 Method and system to encode and decode wide data words  
A parity generation circuit includes a plurality of bit-generation circuits. Each bit-generation circuit receives respective data bits and a respective hard latch signal, and operates to generate a...
7219272 Semiconductor integrated circuit with memory redundancy circuit  
A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error...
7203887 Method and system for routing in low density parity check (LDPC) decoders  
An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are...
Matches 1 - 50 out of 241 1 2 3 4 5 >