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7624332 |
Method for processing noise interference in data accessing device with serial advanced technology attachment interface
A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an...
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7613990 |
Method and system for a multi-channel add-compare-select unit
A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder...
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7610520 |
Digital data signal testing using arbitrary test signal
For testing a digital data signal, a value derived from the digital data signal at a sampling point is compared against a corresponding value of an arbitrary test signal. The comparison is...
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7603596 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
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7581161 |
Method and system for widening the synchronization range for a discrete multitone multicarrier single pilot tone system
A system and method of widening the synchronization range for a discrete multitone multicarrier single pilot tone system includes detecting a first phase error in a received pilot tone; detecting a...
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7546513 |
Circuit and method for checking and recovering a disk array
The present invention is provided for producing check data or recovery data in a disk array. According to the present invention, a plurality of buffers receives and stores the data respectively for...
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7526704 |
Testing system and method allowing adjustment of signal transmit timing
A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which...
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7523365 |
Dynamic determination of signal quality in a digital system
A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the...
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7516379 |
Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)
A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first...
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7512868 |
Method for processing a signal using an approximate map algorithm and corresponding uses
The invention concerns a method for processing a signal using an approximate MAP (maximum a posteriori) algorithm for determining a likelihood ratio Λ k X of a set of states X of a lattice at a...
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7506240 |
Method and apparatus for image processing
The present application relates to a method of at least substantially synchronizing data output from at least first and second graphics cards ( 1, 2 ). A synchronization difference between the...
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7500156 |
Method and apparatus for verifying multi-channel data
A multi-channel data verifying apparatus and method are provided. The apparatus includes a receiver receiving N data channels and a deskew channel generated by sequentially extracting a...
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7484166 |
Semiconductor integrated circuit verification method and test pattern preparation method
In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and...
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7480853 |
Deleting objects from a store of a device
Systems, methods, and computer program products for deleting objects from device stores without deleting corresponding objects from one or more synchronization partners. A device has a device sync...
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7475319 |
Threshold voltage control apparatus, test apparatus, and circuit device
There is provided a threshold voltage control apparatus that controls a threshold voltage for a level comparing section that detects a logic pattern of an input signal by comparing a level of the...
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7472336 |
Data detector and multi-channel data detector
A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections...
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7467335 |
Method and apparatus for synchronizing data channels using an alternating parity deskew channel
The invention includes a method and apparatus for aligning a plurality of data channels using a deskew bitstream. The method includes receiving the deskew bitstream, identifying an aligned deskew...
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7461326 |
Information processing method capable of detecting redundant circuits and displaying redundant circuits in the circuit design process
The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing...
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7461317 |
System and method for aligning a quadrature encoder and establishing a decoder processing speed
A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a...
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7454514 |
Processing data with uncertain arrival time
A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture...
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7447976 |
Data transfer apparatus
A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous...
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7444275 |
Multi-variable polynomial modeling techniques for use in integrated circuit design
Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data...
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7437656 |
Error correction of balanced codeword sequence
A method for recoding an input sequence of words, including assigning a respective bit-grade to at least one of the bits in a first word in the input sequence, deriving candidate words from the...
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7428283 |
Data recovery algorithm using data position detection and serial data receiver adopting the same
The present invention relates generally to a data recovery algorithm and a serial link data receiver adopting the same. The data recovery algorithm includes receiving a serial data stream and a...
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7424307 |
Loss of page synchronization
Systems and methods for maintaining data stream synchronization are provided. A system comprises one or more radio head interface modules and a call processing software module each adapted to...
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7418650 |
Method for temporal synchronization of clocks
In order to carry out in a communication system ( 1 ) a temporal synchronization of clocks in a particularly rapid and efficient manner, a method is proposed which has the following steps:...
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7409631 |
Error-detection flip-flop
An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input...
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7406652 |
Method and circuit for reducing SATA transmission data errors by adjusting the period of sending ALIGN primitives
A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a...
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7404115 |
Self-synchronising bit error analyser and circuit
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator
wherein the generator LFSR generates a first data set which is transmitted through a data bus...
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7370247 |
Dynamic offset compensation based on false transitions
A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment,...
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7370239 |
Input/output device with configuration, fault isolation and redundant fault assist functionality
A process control system includes a plurality of input/output (I/O) devices and a controller in communication using a bus. Each I/O device has an interface for communicatively linking the I/O...
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7366477 |
Redundancy version implementation for an uplink enhanced dedicated channel
This invention describes a method for a redundancy version implementation of an uplink (UL) enhanced dedicated channel (E-DCH) in mobile communication systems by calculating a redundancy version...
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7363431 |
Message-based distributed synchronization in a storage system
Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the...
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7359367 |
Device for preventing erroneous synchronization in wireless communication apparatus
An erroneous synchronization preventing device includes a pattern detector detecting a sync pattern from received data with a broader sync window to output a sync detection notice and a sync...
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7356756 |
Serial communications data path with optional features
Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports...
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7340656 |
Method and apparatus for probing a computer bus
The subject invention facilitates the efficient operation of the disassembly of the microprocessor bus by providing an apparatus and method for detecting and correcting a strobe phase inversion and...
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7330993 |
Slew rate control mechanism
According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the...
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7328396 |
Cyclic redundancy check generating circuit
A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having...
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7308620 |
Method to obtain the worst case transmit data and jitter pattern that minimizes the receiver's data eye for arbitrary channel model
A serial link system is provided for determining a worst-case cumulative data eye. The system includes a transmitter, a receiver, and a channel between the transmitter and receiver such that data...
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7296170 |
Clock controller with clock source fail-safe logic
A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision...
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7296101 |
Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device
A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system...
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7293214 |
Testable design methodology for clock domain crossing
A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals...
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7292668 |
Data processor and data processing method
In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a...
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7290201 |
Scheme for eliminating the effects of duty cycle asymmetry in clock-forwarded double data rate interface applications
A clock management system receives an input clock signal having rising edges and falling edges, a first set of data values associated with the rising edges of the input clock signal, and a second...
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7287200 |
Jitter applying circuit and test apparatus
There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an...
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7284169 |
System and method for testing write strobe timing margins in memory devices
Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the...
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7278071 |
Receiving circuit for receiving message signals
The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled...
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7251772 |
Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing a circuit arrangement of this type
A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the...
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7249304 |
Apparatus and method for error correction in a CDMA mobile communication system
An FEC apparatus and method is provided that uses turbo codes. An input frame is iteratively decoded until an iterative decoding stop command is received under a predetermined control, and the...
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7249292 |
Method for saving power in a user terminal after synchronization loss in broadband wireless access communication system
Disclosed is a method for reducing power consumption of a user terminal when synchronization between a user terminal and a base station is disrupted in a broadband wireless access communication...
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