|
Match
|
Document |
Document Title |
|
|
7240248 |
Apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event
An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an...
|
|
|
7236555 |
Method and apparatus for measuring jitter
In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal...
|
|
|
7234101 |
Method and system for providing data integrity in storage systems
A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate...
|
|
|
7228476 |
System and method for testing integrated circuits at operational speed using high-frequency clock converter
A system tests an integrated circuit at operational speed. The system includes a high frequency clock converter that receives test clock signals at a speed lower than operational speed of the...
|
|
|
7219297 |
Method and device for generating a synchronization variable and the corresponding integrated circuit and digital disc drive
A synchronization variable intended for a second clock signal is generated from a first clock signal and a phase variation signal. A first approximation of the second clock signal is determined,...
|
|
|
7200782 |
Clock recovery system for encoded serial data with simplified logic and jitter tolerance
The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a recovered clock. In order to identify...
|
|
|
7197682 |
Semiconductor test device and timing measurement method
A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings of defined times between...
|
|
|
7194675 |
Backup method, backup system, disk controller and backup program
A backup system includes a first storage device having first storage areas in which an update log of recorded data is stored; a second storage device having second storage areas which are paired...
|
|
|
7185239 |
On-chip timing characterizer
An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement...
|
|
|
7174502 |
Synchronization error detection circuit
Synchronization errors in a received pulse train are detected by detecting rising or falling transitions in the pulse train, generating numbers in a repeating cycle having a length corresponding to...
|
|
|
7174494 |
Method and system for coded null packet-aided synchronization
A communication system comprising a transmitter that is adapted to transmit a data signal that is broken into a plurality of time slots. The transmitter inserts communication data into a subset of...
|
|
|
7168032 |
Data synchronization for a test access port
In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a...
|
|
|
7159137 |
Synchronized communication between multi-processor clusters of multi-cluster computer systems
Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes...
|
|
|
7139289 |
Device and method for error and sync detection
In an error and sync detection circuit, 7-bit byte data is rearranged by a data rearrangement block into 8-bit byte data where 1 byte is comprised of 8 bits. Thereafter, the 8-bit byte data is...
|
|
|
7137058 |
Block synchronization detection apparatus and method
A block synchronization detection apparatus and method. Block synchronization for discriminating one error correction code (ECC) block from another is detected, even when a first sector of the ECC...
|
|
|
7134068 |
Channel processing data without leading sync mark
An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a...
|
|
|
7103827 |
Method and apparatus for detecting start position of code sequence, and decoding method and apparatus using the same
A code sequence start position detection method and apparatus, and a decoding method and apparatus, which can quickly detect the start position of a code sequence by a simple processing...
|
|
|
7089485 |
Simple link protocol providing low overhead coding for LAN serial and WDM solutions
A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during...
|
|
|
7088784 |
Coded modulation for partially coherent systems
A signal constellation is optimized for trellis coded modulation in fast fading channels, where the receiver does not have perfect knowledge of the channel parameters. Specifically, the signal...
|
|
|
7085993 |
System and method for correcting timing signals in integrated circuits
A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system...
|
|
|
7085339 |
Data recovery device
A data recovery device for precisely recovering a transmission signal even if the signal having phase variations is provided. The device comprises a demodulator for demodulating a transmission...
|
|
|
7082556 |
System and method of detecting a bit processing error
The present invention relates generally to an improvement in the ability of test systems to test bit processing capacities of electronic devices, and in particular an improvement in their ability...
|
|
|
7058879 |
Data transmission system, equipment suitable for such a system and data transmission method
A data transmission system is formed by a transmitter ( 50 ) for processing useful data for the purpose of forming series of information signals, and a receiver ( 51 ) for receiving and processing...
|
|
|
7039729 |
Data transfer apparatus
In a data transfer apparatus 10 , first, second, third data transmitters 141, 142, 143 are located in a data transmission device 11 . Data which must not be influenced by delay of transmission...
|
|
|
7024324 |
Delay element calibration
A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference...
|
|
|
7023801 |
Speculative packet selection for transmission of isochronous data
A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control...
|
|
|
7020833 |
Data synchronization detection method, information recording method, and information reproduction method
Data synchronization detection is provided between data identification and code demodulation in a data reproduction system, which performs data synchronization detection using code-modulated data....
|
|
|
7017101 |
Information storage medium, information recording method and information processing method
User information is recorded in each physical sector of an information storage medium in such a style after it is modulated according to a predetermined modulation rule. The physical sector is...
|
|
|
7015836 |
EFM data decoding method and apparatus thereof for optical disk system
An EFM data decoding method and apparatus thereof for optical disk system is provided. According to the method, a 14-bit data complying with the EFM modulation criteria but failing to correspond to...
|
|
|
6980140 |
Flash ADC receiver with reduced errors
Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the...
|
|
|
6976196 |
Error detecting method and device, information storing and reproducing device and magnetic disk drive
In order to precisely detect latent defects where a data-synchronizing signal is to be stored despite changes in the rotation of an information storage medium, a region data detection is used...
|
|
|
6970436 |
Apparatus for monitoring asynchronous transfer mode cells in communication systems
An apparatus for monitoring asynchronous transfer mode cells in the communication system is proper for recognizing state information of asynchronous transfer mode cells transceiving between a base...
|
|
|
6968480 |
Phase adjustment system and method for non-causal channel equalization
A system and method is provided for using phase adjustment in non-causal channel equalization in a communications system. The method comprising: receiving a serial data stream input; comparing a...
|
|
|
6968496 |
Optical disk with error detection code and optical disk apparatus
An optical disk can detect reliable address data without the need of checking the validity of synchronous detection of segment numbers. The optical disk has one or more tracks, and address data is...
|
|
|
6964007 |
Asymmetric error correction apparatus and method, and clock recovering apparatus for optical reading system employing the same
An asymmetric error correction apparatus and method, and clock recovering apparatus and data recovering apparatus for a system for reading data from an optical recording medium such as a CD or DVD...
|
|
|
6952796 |
Test data generating system and method to test high-speed actual operation
A test data generating system and method to conduct high-speed operation (actual operation) test of an LSI using a tester. The system converts existing simulation data to high-speed operation...
|
|
|
6938200 |
Transponder interrogators, radio frequency identification device communication systems, transponder interrogator communication methods, and radio frequency identification device communication methods
The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes...
|
|
|
6920590 |
Semiconductor apparatus for providing reliable data analysis of signals
A semiconductor apparatus is composed of a signal providing circuit and a data analyzer. The signal providing circuit provides an input signal set including at least one input signal. The data...
|
|
|
6920603 |
Path error monitoring method and apparatus thereof
A path error monitoring method is provided for monitoring for an error in a communication path in a synchronous network by using an error detection code inserted into a first predetermined byte in...
|
|
|
6898742 |
System and method for automatic deskew across a high speed, parallel interconnection
A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than...
|
|
|
6895542 |
Data recovery circuit and method and data receiving system using the same
A data recovery circuit for use in a data receiving system to recover an m-bit data stream from an n-bit data stream. The data recovery circuit comprises an n-bit data reconstruction circuit for...
|
|
|
6891406 |
Method and apparatus for supplying a reference voltage for chip-to-chip communication
A method for receiving data by an integrated circuitry chip includes receiving data signals and a first clock signal sent by a sending chip. The data signals are received by data receivers and the...
|
|
|
6892334 |
Method for determining deskew margins in parallel interface receivers
Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur...
|
|
|
6892345 |
Integrated circuit including duplicated synchronous and asynchronous components
An IC including duplicated primary components which can be operated microsynchronously has at least one synchronization device for synchronizing asynchronous signals to the primary clock. An...
|
|
|
6865240 |
Frame synchronizing circuit
The frame synchronizing circuit establishes frame synchronization by detecting a sync pattern laid in an incoming frame. The frame synchronization circuit comprises a first frame synchronizing unit...
|
|
|
6829299 |
Variable length decoder and decoding method
Encoded data using reversible variable length code words is input to a forward decoder ( 123 ) to be decoded in the forward direction. When an error is detected in the encoded data in the forward...
|
|
|
6826719 |
Cellular CDMA transmission system
A telecommunications system and method which includes a transmitter, a first code generator for generating a noise code and a second code generator for generating a string-based code, wherein data...
|
|
|
6819679 |
Multiprotocol packet framing technique
A method and system for packaging frames or packets encoded in a variety of formats, for example, Frame Relay, Ethernet, ATM, or TCP/IP. The method includes: accumulating first and second packets;...
|
|
|
6802034 |
Test pattern generation circuit and method for use with self-diagnostic circuit
A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which...
|
|
|
6774826 |
Synchronization code recovery circuit and method
A circuit which recovers a synchronization code, and a method thereof. Where a synchronization code is not detected from an incoming bitstream, a plurality of synchronization code recovery...
|