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7620883 Techniques for mitigating, detecting, and correcting single event upset effects  
SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and...
7577012 Ferroelectric memory device, method for driving ferroelectric memory device, electronic apparatus, and method for driving electronic apparatus  
A ferroelectric memory device includes: an odd number of memory regions, the odd number being at least three or higher; a readout circuit that reads data of 0 or 1 stored in the odd number of...
7539931 Storage element for mitigating soft errors in logic  
In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output...
7539920 LDPC decoding apparatus and method with low computational complexity algorithm  
Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without...
7536631 Advanced communication apparatus and method for verified communication  
A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word...
7530004 Error correction apparatus using forward and reverse threshold functions  
An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the...
7526037 Reduced complexity detector for multiple-antenna systems  
A reduced-complexity maximum-likelihood detector is disclosed that provides a high degree of signal detection accuracy while maintaining high processing speeds. The detector processes the received...
7512871 Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays  
SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and...
7509567 System and method for resolving data inconsistencies with a data majority  
A system and method for an election and data majority mechanism that solves problems such as bit flipping, mistracking, miscaching, and I/O status errors during real-time operations. Multiple...
7451384 Error recovery in asynchronous combinational logic circuits  
A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results...
7444565 Re-programmable COMSEC module  
A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an...
7428473 Health monitoring in a system of circumvention and recovery  
A system comprises at least one non-hardened processor configured to run a plurality of mission related processes; at least one threat detector configured to detect one or more conditions which...
7424642 Method for synchronization of a controller  
A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary...
7418641 Self-resetting, self-correcting latches  
A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to...
7350136 Voting system for improving the performance of single-user decoders within an iterative multi-user detection system  
A system is presented that provides real-time performance for iterative multi-user detectors, such as Turbo MUDs, which are used to separate simultaneous transmissions on the same frequency, by...
7318175 Memory modeling circuit with fault toleration  
A memory modeling circuit with fault toleration includes a compare circuit, a control circuit and a test circuit. The compare circuit receives the data stored in the same address of memories and...
7308605 Latent error detection  
In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors...
7280468 Apparatus for constant amplitude coded bi-orthogonal demodulation  
A constant amplitude coded bi-orthogonal demodulator demodulates the received constant amplitude bi-orthogonal modulated data, cancels the parity bits to generate the serial data, detects the...
7269780 Power management for circuits with inactive state data save and restore scan chain  
An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the...
7246297 Time-invariant hybrid iterative decoders  
An iterative decoder for receiving a sequence of samples representing a series of symbols, and for decoding the received sequence to the series. The decoder includes a plurality of variable-nodes....
7225394 Voting circuit  
A circuit for correcting errors in an N times duplicated signal is described. The circuit comprises a plurality of AND gates, wherein each of the AND gates comprises a plurality of inputs for...
7215581 Triple redundant latch design with low delay time  
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each...
7185263 Method of joint decoding of possibly mutilated code words  
A method of decoding possibly mutilated code words (r) of a code (C) includes decoding the differences (D) of a number (L−1) of pairs of possibly mutilated code words (r ib , r i+1 ) to obtain...
7107515 Radiation hard divider via single bit correction  
A radiation hard logic device such as a divider is disclosed. The logic device includes a voter module to determine an error free logic device output, a feedback module to generate a correction...
7093189 Method and device for performing soft decision decoding on Reed-Muller codes using decision by majority  
An RM code soft decision decoding method using decision by majority comprises: (a) performing multiplication on a bit group of a codeword, and calculating an information bit's estimate group; (b)...
7089484 Dynamic sparing during normal computer system operation  
A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the...
7071749 Error correcting latch  
An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass...
7065672 Apparatus and methods for fault-tolerant computing using a switching fabric  
Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical...
7054203 High reliability memory element with improved delay time  
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element...
7027333 High reliability triple redundant memory element with integrated testability and voting structures on each latch  
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical...
6993677 System and method for data verification in a RAID system  
The present invention is directed to a system and method for data verification in a RAID system. A method of verifying data in a RAID system may include reading a first item of data from a first...
6981205 Data storage apparatus, read data processor, and read data processing method  
To improve the probability of error correction, thereby generating correct read data. Data is read from the same sector by a number of times and a majority decision is done in the same address,...
6981204 Programmable glitch filter for an asynchronous data communication interface  
An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and...
6977969 Digital FM receiver for recovering FM digital data frame in mobile communication system  
There is provided a digital data receiver for recovering at least one message word signal from a digital data frame. The digital receiver includes a digital FM demodulator for receiving frequency...
6941506 Switching circuit for decoder  
A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome...
6938183 Fault tolerant processing architecture  
A fault tolerant processing circuit comprising at least three processor groupings, a synchronizing circuit and a fault logic circuit. Each of the processor groupings have a plurality of processor...
6928606 Fault tolerant scan chain for a parallel processing system  
A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains...
6928605 Add-compare-select accelerator using pre-compare-select-add operation  
How a first result of a first operation compares to a second result of a second operation is identified. The identification may be performed without producing the first result or the second result....
6920599 Storage device and error correction method thereof  
Positions in which errors have occurred are found more accurately and erasure correction is performed more effectively than in cases where TA flags or error flags issued by the R/W channel are...
6854081 Initializing/diagnosing system in on-chip multiprocessor system  
A semiconductor chip of the present invention includes a plurality of first elements each of which diagnoses itself, and a second element which inputs diagnosis results from the first elements and...
6831496 Error correcting latch  
An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass...
6828693 Electric circuit  
An electric circuit for a vehicle electrical system powered by a voltage supply. The circuit includes a control stage having a switching device, a switching module, a signal output, and a...
6772392 Image failure detection unit in redundant duplex transmission  
There is provided an image failure detection unit in redundant duplex transmission in which a failure occurring on a regular link is detected at in real time, and the link is instantaneously...
6772368 Multiprocessor with pair-wise high reliability mode, and method therefore  
In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation....
6763481 Data processor  
A data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic...
6637005 Triple redundant self-scrubbing integrated circuit  
A fault tolerant integrated circuit employs triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The integrated circuit includes three or more...
6609185 Data storage system having majority gate filter  
An arbitration system having a common resource and a first arbitration logic. The first arbitration logic includes a plurality of logic sections. Each one of the logic sections is fed a...
6578161 Counting apparatus, counting method, and computer readable storage medium  
A counting apparatus comprising an execution detection circuit for detecting the execution of a predetermined operation; plural memory circuits for commonly storing the information on the number of...
6532550 Process protection system  
A protection system for a complex process has four redundant protection sets, each of which produces partial reactor trip and partial safeguard actuation signals in pairs of microprocessor-based...
6523148 Majority decision method for improved frame error rate in the digital enhanced cordless telecommunications system  
A majority decision method for improved frame error rate in the digital enhanced cordless telecommunications (DECT) system. Specifically, one embodiment of the present invention includes a method...
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