Matches 1 - 50 out of 315 1 2 3 4 5 6 7 >
Match Document Document Title
7634709 Familial correction with non-familial double bit error detection  
Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16...
7624330 Unified memory architecture for recording applications  
An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error...
7620879 Method of detecting occurrence of error event in data and apparatus for the same  
A method of detecting an occurrence of an error event in data and an apparatus for the same are provided. The method includes: preparing an error detection code wherein syndrome sequences for...
7613988 Degree limited polynomial in Reed-Solomon decoding  
Processing Reed Solomon data is disclosed. A scratch polynomial having a degree is obtained using an inversionless Berlekamp-Massey process. The degree of the scratch polynomial is limited. A...
7607071 Error correction using iterating generation of data syndrome  
An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word...
7607068 Apparatus and method for generating a Galois-field syndrome  
The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first...
7607074 Error detecting code addition circuit, error detection circuit and method, and disc apparatus  
An error detector includes a substitute value output section outputting a specific substitute value corresponding to an encoding byte sequence Q of input byte data by referring to a table storing,...
7600177 Delta syndrome based iterative Reed-Solomon product code decoder  
A method for generating syndromes for a data block is disclosed. The method generally includes the steps of (A) calculating a plurality of row syndromes and a plurality of column syndromes for the...
7594156 High-efficiency compact turbo-decoder  
A circuit and a method for decoding data coded by blocks by a turbo-code including successive steps. One of the steps may use n first processors adapted to operating in parallel on n lines, or...
7590924 Architecture and control of Reed-Solomon list decoding  
Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide...
7590047 Memory optimization packet loss concealment in a voice over packet network  
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals. A voice playout unit in the receiver...
7587658 ECC encoding for uncorrectable errors  
An error detecting and correcting method and mechanism. An error correcting code for data is utilized wherein a special syndrome pattern is used to indicate corresponding data includes a previously...
7565587 Background block erase check for flash memories  
Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check...
7562282 Disk drive employing error threshold counters to generate an ECC error distribution  
A disk drive is disclosed comprising a head actuated over a disk. A redundancy generator generates a plurality of redundancy symbols appended to user data to form a codeword C(x) written to a...
7562283 Systems and methods for error correction using binary coded hexidecimal or hamming decoding  
Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one...
7546517 Error-correcting circuit for high density memory  
This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type...
7543220 Control method for error detection & correction apparatus, error detection & correction apparatus, and computer-readable storage medium storing control program for error detection & correction apparatus  
The present invention provides a control method for an error detection & correction apparatus, comprising a plurality of data processing apparatuses which reside in a data communications path and...
7543215 Integrated apparatus for multi-standard optical storage media  
An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD)...
7539929 Error correction for data communication  
Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of...
7530009 Data storage method and data storage device  
A data storage device comprising a disk storage medium containing user data in a plurality of sectors wherein each of the plurality of sectors comprises a subdivision of a track, a head for writing...
7526716 Recording/regenerating device, method of encoding error correction, method of recording data  
Embodiment of the invention is to make the number of interleave sequences and the number of redundant bits as small as possible without increasing the number of bits per symbol so much. By encoding...
7526713 Low power cost-effective ECC memory system and method  
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from...
7509566 Flash memory  
A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an...
7502986 Method and apparatus for collecting failure information on error correction code (ECC) protected data  
A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result,...
7496825 CRC-based error correction  
An ordered list of CRC syndromes, corresponding to single-bit errors, is used to identify an error bit position, enabling correction of the bit at the identified error bit position. For instance,...
7496826 Method, system, and apparatus for adjacent-symbol error correction and detection code  
A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases among other techniques are described. In one embodiment,...
7496822 Apparatus and method for responding to data retention loss in a non-volatile memory unit using error checking and correction techniques  
In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking and correction techniques, a...
7478311 Error detection device and error detection method  
In an error detection method of the present invention, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target...
7475329 Techniques for performing Galois field logarithms for detecting error locations that require less storage space  
To perform error detection and correction on a data sector, syndromes are calculated and used to determine error values and error locations. Logarithmic calculations in Galois field need to be...
7472334 Efficient method for the reconstruction of digital information  
Improved method of encoding and repairing data for reliable storage and transmission using erasure codes, which is efficient enough for implementation in software as well as hardware. A systematic...
7464323 Algebraic geometric code adapted to error bursts  
The present invention concerns channel codes particularly well adapted to transmission in channels in which errors tend to occur in bursts. Moreover, the codes according to one embodiment of the...
7447982 BCH forward error correction decoder  
An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four...
7441175 Turbo product code implementation and decoding termination method and apparatus  
A method of decoding a turbo product code (TPC) code word comprises iteratively decoding the TPC code word using an iterative decoder. The method further comprises terminating the iterative...
7437653 Erased sector detection mechanisms  
The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits,...
7426674 Method of computing partial CRCs  
Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result,...
7426678 Error checking parity and syndrome of a block of data with relocated parity bits  
Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value....
7421642 Method and apparatus for error detection  
The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically,...
7421640 Method and apparatus for providing error correction capability to longitudinal position data  
A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words....
7409629 Methods and devices for decoding one-point algebraic geometric codes  
A method of decoding a one-point algebraic geometric code of dimension k and length n, in which, in order to identify the position of the errors in a received word, the syndromes matrix S, of size...
7392461 Decoding for algebraic geometric code associated with a fiber product  
The present invention concerns a method and apparatus of decoding a one-point algebraic geometric code defined on an algebraic curve represented by an equation in X and Z of degree 2 μφ in Z,...
7389469 Bus systems, apparatuses, and methods of operating a bus  
Data transmission between transmitting/receiving nodes in a bus system may be controlled based on an error check of received data. When an error in the received data is detected, the transmitting...
7353446 Cyclic redundancy check circuit for use with self-synchronous scramblers  
The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit...
7353449 Method of soft-decision decoding of Reed-Solomon codes  
The invention relates to a Reed-Solomon decoder and to a method of soft decision decoding of Reed-Solomon codes, wherein a syndrome polynomial, an erasure polynomial, and a modified syndrome...
7328397 Method for performing error corrections of digital information codified as a symbol sequence  
A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to...
7272777 Method for correcting a burst of errors plus random errors  
An efficient method for finding all the possible corrections of a bust of length b and e random errors consists of finding a polynomial whose roots are the candidate location for l—the location...
7246292 Apparatus and method for bit pattern learning and computer product  
A computer calculates bit patterns of syndromes for all candidate bit patterns of reception words that are input in ECC-EOR circuits of a logic circuit. The bit patterns of the syndromes are stored...
7243293 (18, 9) Error correction code for double error correction and triple error detection  
An (18, 9) error correction code that is simultaneously double error correcting and triple error detecting is disclosed. The code is defined by the following parity check matrix: β 1 3 ⁢ ⁢...
7237183 Parallel decoding of a BCH encoded signal  
A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial format to produce a received...
7228490 Error correction decoder using cells with partial syndrome generation  
A decoder to correct errors in data includes a plurality of cells. Each cell generates a partial syndrome based on data blocks and one or more redundancy blocks. Each cell generates a partial error...
7225386 High-efficiency error detection and/or correction code  
Error detection and correction codes are provided. For a word of m bits that is to be coded, a vector with m components, each component corresponding to a bit of the word, is formed. The vector is...
Matches 1 - 50 out of 315 1 2 3 4 5 6 7 >