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8700688 Polynomial data processing operation  
A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a...
8694855 Error correction code technique for improving read stress endurance  
A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors...
8694879 Efficient use of CRC with limited data  
An automotive sensor reads from memory previously stored back-calculated diagnostic-code values for which a fixed cyclic-redundancy-check (“CRC”) value is valid and transmits the previously sto...
8694873 Memory system and error correction method  
Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected...
8689089 Method and system for encoding for 100G-KR networking  
Various examples are provided for encoding for 100G-KR networking. In one example, among others, a coding method uses certain forward error correcting codes based on a given transcoding method and...
8689088 Method of encoding data using a low density parity check code  
A method for encoding data using a parity check matrix is disclosed. The method for encoding data using a parity check matrix comprises generating a fourth base matrix by applying a row permutation...
8689083 Rate-compatible protograph LDPC codes  
Digital communication coding methods resulting in rate-compatible low density parity-check (LDPC) codes built from protographs. Described digital coding methods start with a desired code rate and a...
8689078 Determining a message residue  
A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments...
8681698 Rate matching for wideband code division multiple access  
Described embodiments provide a wideband code division multiple access (W-CDMA) system that employs a rate matching rule having a modified puncturing algorithm. The modified puncturing algorithm...
8675756 Method for identifying received symbols corrupted by burst noise and related device  
A method for identifying a corrupted received signal that includes symbols is described. Each symbol may have a value of a Galois field associated therewith. The receiver may be configured to store...
8677221 Partial voltage read of memory  
A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital...
8677213 Electronic device comprising error correction coding device and electronic device comprising error correction decoding device  
An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder...
8671327 Method and system for adaptive coding in flash memories  
To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter,...
8667376 Decoding device, data communication apparatus having the decoder device, and data memory  
A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator...
8656260 Methods and circuits for processing a data block by frames  
Methods and circuits process a data block of first bits. A circuit includes a register and a parallel combiner. The register is configured to store second bits. The second bits are iteratively a...
8656263 Trellis-coded modulation in a multi-level cell flash memory device  
A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory...
8656247 Apparatus and method for encoding and decoding block low density parity check codes with a variable coding rate  
A matrix multiplier multiplies the signal output from a first adder by an inverse matrix T−1 of a partial matrix T of a parent parity check matrix, and outputs the multiplication result to a f...
8650466 Incremental generation of polynomials for decoding reed-solomon codes  
An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within...
8650467 Parallel chien search over multiple code words  
A method for decoding an ECC, in a decoder that includes at least first and second root search units, includes accepting at least first and second Error Locator Polynomials (ELPs) that have been...
8644434 Apparatus and methods for performing sequence detection  
An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of...
8645807 Apparatus and method of processing polynomials  
An apparatus of processing polynomials includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The...
8645788 Forward error correction (FEC) convergence by controlling reliability levels of decoded words in a soft FEC decoder  
A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the...
8640011 Single CRC polynomial for both turbo code block CRC and transport block CRC  
Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels...
8640000 Nested coding techniques for data storage  
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of...
8631307 Method for encoding and/or decoding multimensional and a system comprising such method  
A method and a system of multidimensional encoding and/or decoding to be processed by a computer or a digital hardware system. The method utilizes an error correcting code which is chosen from the...
8627167 Methods and apparatus for providing multi-layered coding for memory devices  
Systems and methods are provided for recovering data stored in memory. A group of data is encoded using a first layer of code to form a first encoded group of data. Individual portions of the first...
8621329 Reconfigurable BCH decoder  
An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a...
8621328 Wear-focusing of non-volatile memories for improved endurance  
Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into...
8621330 High rate locally decodable codes  
Data storage techniques and solutions simultaneously provide efficient random access to information and high noise resilience. The amount of storage space utilized is only slightly larger than the...
8621332 Word-serial cyclic code encoder  
A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code...
8621331 Continuous parallel cyclic BCH decoding architecture  
Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants...
8621290 Memory system that supports probalistic component-failure correction with partial-component sparing  
A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an...
8612835 Cyclic shift device, cyclic shift method, LDPC decoding device, television receiver, and reception system  
The present invention relates to using a barrel shifter in a cyclic shift device for an LDPC decoding device, a television receiver, and/or a reception system, whereby reduction in size of the...
8612826 Systems and methods for non-binary LDPC encoding  
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.
8612842 Apparatus for generating a checksum  
An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload...
8612834 Apparatus, system, and method for decoding linear block codes in a memory controller  
Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory,...
8607129 Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic  
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
8607125 Basic matrix based on irregular LDPC, codec and generation method thereof  
The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any column element of i, j, k or l...
8601339 Layered coding techniques for data storage  
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of...
8595602 Configurable encoder for cyclic error correction codes  
Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first...
8595584 Method and apparatus for interleaving a data stream using quadrature permutation polynomial functions (QPP)  
A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation...
8583991 High density multi-level memory  
Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments...
8583994 Coding apparatus and method for handling quasi-cyclical codes  
Disclosed herein is a coding apparatus handling quasi-cyclic codes in which a given code word cyclically shifted by p symbols provides another code word, wherein parallel processing is executed in...
8578249 LDPC encoding and decoding of packets of variable sizes  
Techniques to support low density parity check (LDPC) encoding and decoding are described. An apparatus includes at least one processor and a memory coupled to the at least one processor. The at...
8572468 Method for transmitting a binary information word  
A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the...
8572461 Feedback signaling error detection and checking in MIMO wireless communication systems  
A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC...
8566679 Error-correcting encoding method with total parity bits, and method for detecting multiple errors  
An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of...
8566680 Systems, methods and computer program products including features for coding and/or recovering data  
Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data....
8555128 System and method for transmitting and receiving acknowledgement information  
A system and method for transmitting and receiving acknowledgement information are provided. A method for communications device operations includes determining a hybrid automatic repeat request...
8555148 Methods and apparatus to generate multiple CRCs  
Methods and apparatus for generating cyclic redundancy checks (CRCs). In one aspect of the present invention, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits...