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8832535 Word-serial cyclic code encoder  
A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code...
8832523 Multi-state symbol error correction in matrix based codes  
Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated...
8819528 Encoder, decoder, and encoding method  
An encoder and decoder using LDPC-CC are provided, which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an...
8819331 Memory system and memory controller  
A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which...
8812938 Coding apparatus, coding method, decoding apparatus, decoding method, program and transmission system  
Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the...
8793559 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
A method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. In one...
8788915 Apparatuses and methods for encoding using error protection codes  
Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.
8782493 Correcting data in a memory  
Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or...
8782494 Reproducing data utilizing a zero information gain function  
A method begins by a dispersed storage (DS) processing module receiving a zero information gain (ZIG) encoded data slice and a subset of encoded data slices of a set of encoded data slices. The...
8775894 Lane specific CRC  
A method of data validation is provided. In one implementation, the method includes performing a cyclic redundancy check (CRC) on data transmitted over a channel having L lanes. In one...
8775912 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
8775910 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
8775897 Data processing system with failure recovery  
Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data...
8775893 Variable parity encoder  
An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a...
8775911 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
8769385 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
8769386 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
8766662 Integrity checking of configuration data of programmable device  
Methods and a system for operating a programmable device are disclosed. In one embodiment, a method includes accessing a master summary data and loading an original configuration data to...
8769380 Methods and apparatus for error recovery in memory systems employing iterative codes  
Systems and methods for error recovery are presented. Data is decoded with an iterative decoding scheme having a first set of parameters. In response to a determination that the iterative decoding...
8762818 System and methods for performing decoding error detection in a storage device  
System and methods for performing decoding error detection in a storage device are provided. Data bits of a data polynomial may be retrieved from a storage device. The data bits may be arranged in...
8750223 Method for transmitting control information in wireless communication system and apparatus therefor  
A method for transmitting information data by using a Reed-Muller coding scheme in a wireless communication system is disclosed. The method includes the steps of dividing the information data to...
8745471 Low-density parity-check convolutional code (LDPC-CC) encoding method, encoder and decoder  
An encoding method and an encoder for creating a low-density parity check convolution code (LDDC-CC), sending a signal sequence after subjecting the code to an error-correction using the...
8745460 Encoding/decoding apparatus and method  
An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each variable...
8745476 Systems and methods for cyclic redundancy check implementation  
In accordance with the teachings described herein, systems and methods are provided for calculating a Cyclic Redundancy Check (CRC) code for a message. A system includes a first CRC calculator and...
8737541 Decoding apparatus, decoding method and recording medium  
Provided is a decoding apparatus capable of reducing the error rate of the decoding results and also the circuit scale. A computing unit computes a plurality of distances only for a number of code...
8739005 Error correction encoding apparatus, error correction decoding apparatus, nonvolatile semiconductor memory system, and parity check matrix generation method  
According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme...
8732563 Method for mapping and de-mapping of non-binary symbols in data communication systems  
A method of de-mapping non-binary Galois field symbols from physical layer code-words in a data communication system, in which at least one physical layer code-word includes portions mapped from...
8719669 Error correction decoder and error correction method thereof  
An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data,...
8719678 Configurable encoder for cyclic error correction codes  
Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first...
8713416 Performing a cyclic redundancy checksum operation responsive to a user-level instruction  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
8713415 Method for generating codewords  
Provided is a method for generating codewords. The method comprises the following steps: receiving an information bit; generating a generating matrix in which a size of a column is identical with a...
8707129 Feedback signaling error detection and checking in MIMO wireless communication systems  
A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC...
8700688 Polynomial data processing operation  
A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a...
8694855 Error correction code technique for improving read stress endurance  
A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors...
8694879 Efficient use of CRC with limited data  
An automotive sensor reads from memory previously stored back-calculated diagnostic-code values for which a fixed cyclic-redundancy-check (“CRC”) value is valid and transmits the previously sto...
8694873 Memory system and error correction method  
Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected...
8689089 Method and system for encoding for 100G-KR networking  
Various examples are provided for encoding for 100G-KR networking. In one example, among others, a coding method uses certain forward error correcting codes based on a given transcoding method and...
8689088 Method of encoding data using a low density parity check code  
A method for encoding data using a parity check matrix is disclosed. The method for encoding data using a parity check matrix comprises generating a fourth base matrix by applying a row permutation...
8689083 Rate-compatible protograph LDPC codes  
Digital communication coding methods resulting in rate-compatible low density parity-check (LDPC) codes built from protographs. Described digital coding methods start with a desired code rate and a...
8689078 Determining a message residue  
A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments...
8681698 Rate matching for wideband code division multiple access  
Described embodiments provide a wideband code division multiple access (W-CDMA) system that employs a rate matching rule having a modified puncturing algorithm. The modified puncturing algorithm...
8675756 Method for identifying received symbols corrupted by burst noise and related device  
A method for identifying a corrupted received signal that includes symbols is described. Each symbol may have a value of a Galois field associated therewith. The receiver may be configured to store...
8677221 Partial voltage read of memory  
A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital...
8677213 Electronic device comprising error correction coding device and electronic device comprising error correction decoding device  
An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder...
8671327 Method and system for adaptive coding in flash memories  
To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter,...
8667376 Decoding device, data communication apparatus having the decoder device, and data memory  
A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator...
8656260 Methods and circuits for processing a data block by frames  
Methods and circuits process a data block of first bits. A circuit includes a register and a parallel combiner. The register is configured to store second bits. The second bits are iteratively a...
8656263 Trellis-coded modulation in a multi-level cell flash memory device  
A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory...
8656247 Apparatus and method for encoding and decoding block low density parity check codes with a variable coding rate  
A matrix multiplier multiplies the signal output from a first adder by an inverse matrix T−1 of a partial matrix T of a parent parity check matrix, and outputs the multiplication result to a f...
8650466 Incremental generation of polynomials for decoding reed-solomon codes  
An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within...