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9043669 Distributed ECC engine for storage media  
Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an...
8984376 System and method for avoiding error mechanisms in layered iterative decoding  
A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are...
8918702 Semiconductor memory having non-standard form factor  
A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to...
8719669 Error correction decoder and error correction method thereof  
An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data,...
8717966 Symmetrical cooperative diversity in the relay-enabled wireless systems  
A communications system includes a source, a destination, and multiple relays. In a first time period, the source emits a first transmission and a first relay retransmits a prior source...
8627174 Memory devices and systems including error-correction coding and methods for error-correction coding  
In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives...
8533568 LDPC encoding methods and apparatus  
A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure...
8533571 Lossy coding of signals  
A method is described for packing variable-length entropy coded data into a fixed rate data stream along with resolution enhancement data, the method providing tightly constrained propagation of...
8533570 Magnetic recording apparatus  
According to one embodiment, there is provided a magnetic recording apparatus configured to record data subjected to error correcting coding according to a shingled recording scheme, the magnetic...
8473808 Semiconductor memory having non-standard form factor  
A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to...
8448256 Secure partitioning of programmable devices  
According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores...
8392805 Non-MDS erasure codes for storage systems  
Erasure-encoded data is stored across a plurality of storage devices in a data storage system. The erasure-encoded data includes k data elements to store on k data storage devices and m parity...
8307264 Detection apparatus  
A detection apparatus detecting an error component contained in two signals (A, B) approximated by a cosine and sine functions representing an object position, the detection apparatus including an...
7987412 Reed Solomon decoding of signals having variable input data rates  
A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two...
7949933 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of...
7673219 Cooperative relay networks using rateless codes  
A system and method for communicating information in a wireless cooperative relay network of nodes, the nodes including a source, a set of relays, and a destination. The source broadcasts a code...
7646835 Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device  
A method for automatically calibrating intra-cycle timing relationships between command signals, data signals, and sampling signals for an integrated circuit device. The method includes generating...
7634707 Error detection/correction method  
A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a...
7634709 Familial correction with non-familial double bit error detection  
Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16...
7613980 System for computing a CRC value by processing a data message a word at a time  
A system for computing a CRC value includes at least one memory for storing a data message, a current CRC value, and a plurality of lookup tables. The data message includes a plurality of words,...
7512867 Method for encoding/decoding error correcting code, transmitting apparatus and network  
A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code...
7428692 Parallel precoder circuit  
A parallel precoder circuit executes a differential encoding operation on an n-row parallel input information series, and outputs an n-row parallel output information series, where 2≦n. Output...
7331011 Semiconductor integrated circuit device  
A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of...
7305593 Memory mapping for parallel turbo decoding  
A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply...
7299399 Method and apparatus for parallelly processing data and error correction code in memory  
A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first...
7206962 High reliability memory subsystem using data error correcting code symbol sliced command repowering  
A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into...
7181673 Codeword for use in digital optical media and a method of generating therefor  
A codeword for use in error correction of digital optical media, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word which can...
7149932 Serial communication device and method of carrying out serial communication  
A serial communication device bridging between a parallel bus and a serial bus, includes (a) a check bit producer which applies an error correcting code to parallel data transmitted through the...
7137045 Decoding method and apparatus therefor  
A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction,...
7051265 Systems and methods of routing data to facilitate error correction  
Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single...
6986095 Error correction device  
For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same...
6856625 Apparatus and method of interleaving data to reduce error rate  
A method and apparatus for reducing the information error rate of a communication network. The apparatus comprises a selector device coupled to a Framer and to an Interleaver. The selector device...
6760881 Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)  
A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes...
6691276 Method for detecting and correcting failures in a memory system  
According to one embodiment, a method is disclosed. The method includes interleaving a first error correction code with a second error correction code to generate a third error correction code...
6684363 Method for detecting errors on parallel links  
System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an...
6640326 Data set recovery by codeword overlay  
A method for recovering user data from a host device stored on a data storage medium where a said data may become corrupted during a read operation comprises: performing a read operation to read...
6578136 Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit  
A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least...
6459957 Programmable smart membranes and methods therefor  
A programmable smart membrane and methods therefor. The smart membrane conducts an overall function on at least one of a sorting function, a filtering function and an absorbing function of at...
6079044 Method and error correcting code (ECC) apparatus for storing predefined information with ECC in a direct access storage device  
Apparatus and methods for storing predefined information with error correcting code (ECC) in a direct access storage device are provided. Predetermined information is identified and loaded to an...
6052818 Method and apparatus for ECC bus protection in a computer system with non-parity memory  
An apparatus and method in which ECC bus protection capability can be generated on a memory card in conjunction with a computer system with a built-in ECC capability to reduce data transmission...
5933436 Error correction/detection circuit and semiconductor memory device using the same  
An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size...
5896404 Programmable burst length DRAM  
A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in...
5818855 Galois field multiplier for Reed-Solomon decoder  
A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first...
5781568 Error detection and correction method and apparatus for computer memory  
An S8ED system is implemented in a memory system to detect single errors involving one or more bits in a byte of subject data, stored in and retrieved from the memory system. Relationships between...
5757823 Error detection and correction for four-bit-per-chip memory system  
Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a...
5754563 Byte-parallel system for implementing reed-solomon error-correcting codes  
A high-speed byte-parallel pipelined error-correcting system for Reed-Solomon codes includes a parallelized and pipelined encoder and decoder and a feedback failure location system. Encoding is...
5491703 Cam with additional row cells connected to match line  
A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least...
5450424 Semiconductor memory device with error checking and correcting function  
A memory cell array is divided into a plurality of subregions along row and column directions. In data reading, 1-bit memory cell is selected from each of the subregions which are arranged on...
5375127 Method and apparatus for generating Reed-Soloman error correcting code across multiple word boundaries  
An error correction code (ECC) generator/checker for processing high bandwidth data block transfers. The high bandwidth ECC generator/checker logic includes a plurality stages, each stage...
5307356 Interlocked on-chip ECC system  
An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system...

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