|
Match
|
Document |
Document Title |
|
|
7620876 |
Reducing false positives in configuration error detection for programmable devices
A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device...
|
|
|
7620875 |
Error correction code memory system with a small footprint and byte write operation
A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory...
|
|
|
7617437 |
Error correction device and method thereof
A device for error correction includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so...
|
|
|
7616484 |
Soft errors handling in EEPROM devices
Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its...
|
|
|
7610542 |
Semiconductor memory in which error correction is performed by on-chip error correction circuit
A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is...
|
|
|
7610541 |
Computer compressed memory system and method for storing and retrieving data in a processing system
A computer compressed memory system for storing and retrieving data in a processing system, includes a memory including at least one memory device for storing at least one of uncompressed data and...
|
|
|
7609777 |
Maximum likelihood a posteriori probability detector
A communication device comprising an ML-APP detector coupled to at least two antennas. The ML-APP detector comprises at least one Hx unit coupled to at least one LLR unit. The Hx unit generates a...
|
|
|
7607067 |
Method and apparatus for accessing memory
A two-dimensional array is stored in a first storage memory. A data accessing direction of the first storage memory is in a row direction. A method for reading data in the two-dimensional array in...
|
|
|
7606222 |
System and method for increasing the range or bandwidth of a wireless digital communication network
A system and method, associated with a receiver, for increasing the range or bandwidth of a wireless digital communication network and a receiver incorporating the system or the method. In one...
|
|
|
7603609 |
Method and system for optimized instruction fetch to protect against soft and hard errors
A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is...
|
|
|
7603592 |
Semiconductor device having a sense amplifier array with adjacent ECC
A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system...
|
|
|
7596738 |
Method and apparatus for classifying memory errors
One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory...
|
|
|
7594158 |
Parity error checking and compare using shared logic circuitry in a ternary content addressable memory
Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles...
|
|
|
7590919 |
Apparatus, method and computer program product for reading information stored in storage medium, and storage medium for storing information based on charge amount
A reproducing apparatus includes a storage unit including a plurality of memory elements each capable of holding an electric charge, each memory element indicating a 2-bit code which is related to...
|
|
|
7590918 |
Using a phase change memory as a high volume memory
A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the...
|
|
|
7590913 |
Method and apparatus of reporting memory bit correction
Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of...
|
|
|
7587658 |
ECC encoding for uncorrectable errors
An error detecting and correcting method and mechanism. An error correcting code for data is utilized wherein a special syndrome pattern is used to indicate corresponding data includes a previously...
|
|
|
7587655 |
Method of transferring signals between a memory device and a memory controller
Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are...
|
|
|
7586993 |
Interleaver memory selectably receiving PN or counter chain read address
A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of interleaving as defined in the IS-2000...
|
|
|
7586099 |
Vacuum plasma generator
A vacuum plasma generator (VPG) includes an output connector for electrical connection of the VPG to at least one electrode of a plasma chamber. The VPG includes a mains connector for connection of...
|
|
|
7581153 |
Memory with embedded error correction codes
A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for...
|
|
|
7577809 |
Content control systems and methods
A control system comprises an interface configured to receive a content request from a request source wherein the content request identifies content stored on a storage medium. The control system...
|
|
|
7571379 |
Method and system for configuring registers in microcontrollers, and corresponding computer-program product
A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic...
|
|
|
7571371 |
Parallel parity checking for content addressable memory and ternary content addressable memory
Methods and arrangements for parallel parity checking for content addressable memory and ternary content addressable memory during compare cycles are disclosed. Further, methods and arrangements...
|
|
|
7571357 |
Memory wrap test mode using functional read/write buffers
A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby...
|
|
|
7570447 |
Storage control device and method for detecting write errors to storage media
There are provided a cache region that stores write data from a host device, storage media, a data storage region for the storage media, and a comparison unit. A first comparison object is...
|
|
|
7568228 |
Intrusion detection in data processing systems
Described is apparatus for testing an intrusion detection system in a data processing system. The apparatus comprises an attack generator for generating attack traffic on a communications path in...
|
|
|
7568146 |
Semiconductor storage device and pseudo SRAM
To provide a semiconductor storage device capable of reducing the number of ECC bits. A semiconductor storage device according to an embodiment of the invention includes a memory cell array, an ECC...
|
|
|
7565602 |
Memory error detection device and method for detecting a memory error
A memory error detection device for a memory having cells arranged in memory rows and columns, wherein the memory is occupied such that the protection memory row or column has a predetermined...
|
|
|
7565597 |
Fast parity scan of memory arrays
A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data...
|
|
|
7565596 |
Data recovery systems
Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a...
|
|
|
7565587 |
Background block erase check for flash memories
Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check...
|
|
|
7555699 |
Storage control circuit, and method for address error check in the storage control circuit
A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address...
|
|
|
7551478 |
Apparatus, method and computer program product for reading information stored in storage medium
An apparatus for reproducing information includes a memory unit which stores charge; a reading unit which obtains an amount of the charge stored in the memory unit, and reads information by...
|
|
|
7549109 |
Memory circuit, such as a DRAM, comprising an error correcting mechanism
A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing...
|
|
|
7546515 |
Method of storing downloadable firmware on bulk media
A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and the parity data is stored with the portions...
|
|
|
7546514 |
Chip correct and fault isolation in computer memory systems
Systems and methods for implementing chip correct and fault isolation in computer memory systems are disclosed. An exemplary method may include interleaving check bits with a data word to form at...
|
|
|
7543218 |
DVD decoding method and apparatus using selective po-correction
A method of decoding DVD-format data may include: receiving a demodulated error correction code (ECC) block of DVD-format data; parity-of-inner-code-correcting (PI-correcting) the demodulated ECC...
|
|
|
7543216 |
Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises providing serial data stream into the FPGA from an external source, loading data...
|
|
|
7543215 |
Integrated apparatus for multi-standard optical storage media
An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD)...
|
|
|
7543211 |
Toggle memory burst
A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to...
|
|
|
7536627 |
Storing downloadable firmware on bulk media
A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and parity data is stored with the portions of...
|
|
|
7533330 |
Redundancy for storage data structures
A storage device comprising has a storage medium, a read-write mechanism, an object-based file system interface, and a controller. The read-write mechanism is adapted to read and to write data from...
|
|
|
7533322 |
Method and system for performing function-specific memory checks within a vehicle-based control system
Integrity of data stored in a memory space associated with a vehicle-based control system (such as a traction enhancement system) is verified through the use of sub-module checksums. A checksum for...
|
|
|
7533321 |
Fault tolerant encoding of directory states for stuck bits
A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the...
|
|
|
7530009 |
Data storage method and data storage device
A data storage device comprising a disk storage medium containing user data in a plurality of sectors wherein each of the plurality of sectors comprises a subdivision of a track, a head for writing...
|
|
|
7530005 |
Storage device
The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read...
|
|
|
7529985 |
Memory size allocation device and method for interleaving
A method and device for interleaving the (N+1) input data and for allocating the corresponding memory comprises the steps of allocating a m th buffer section equals to (m×Dm+Pm) memory address...
|
|
|
7526713 |
Low power cost-effective ECC memory system and method
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from...
|
|
|
7526692 |
Diagnostic interface architecture for memory device
A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from...
|