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7269759 Data processing apparatus and method for handling corrupted data values  
The present invention provides a data processing apparatus and method for handling corrupted data values. The method comprises the steps of: a) accessing a data value in a memory within a data...
7266724 Apparatus and method for interruption of read and write operation and program storage medium for storing read and write procedure program  
A method and an apparatus for performing high-quality read and write operations through a simple operation without being affected by an interruption even when the interruption has occurred in the...
7263649 Converting circuit for preventing wrong error correction codes from occurring due to an error correction rule during data reading operation  
A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes...
7263648 Apparatus and method for accommodating loss of signal  
A memory control system for a network that broadcasts to multiple terminals content data including music, video and the like, and also including commercial advertisements. A memory in the terminal...
7260848 Hardened extensible firmware framework  
A method for hardening an extensible firmware framework and system in which the framework is implemented. In accordance with the method, a resource access policy that defines rules to allow or...
7256989 Removable hard disk housing assembly  
The removable hard disk housing assembly includes a housing substrate, a hard disk supporting frame, a rotatable handle, a supporting piece, two plates-liked elements and two springs. The hard disk...
7257762 Memory interface with write buffer and encoder  
A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data...
7257761 Method for preventing read errors in optical disc drive  
A method for improving data accuracy and data flow of a disc servo system to read data on a disk. First of all, a read mode of the disc servo system is determined. If the read mode is an...
7251773 Beacon to visually locate memory module  
One embodiment disclosed relates to a method of visually locating a memory module. An electronic communication is received by circuitry on the memory module to be visually located. A beacon state...
7249308 Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O firewalls  
A system for testing logical partitioning. In a preferred embodiment, an I/O adapter is configured to break partitioning rules, for example, to attempt to access addresses outside a valid address...
7246300 Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation  
FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status...
7243290 Data encoding for fast CAM and TCAM access times  
A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an...
7243277 Method of combining multilevel memory cells for an error correction scheme  
A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature...
7240254 Multiple power levels for a chip within a multi-chip semiconductor package  
A semiconductor memory chip is provided for packaging along with a system chip in a single semiconductor package having a plurality of external connectors. The memory chip includes a memory storage...
7237175 Memory circuit  
When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to...
7233612 Wireless communication deinterleaver using multi-phase logic and cascaded deinterleaving  
A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with...
7231580 Nonvolatile memory apparatus and data processing system  
The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error...
7222271 Method for repairing hardware faults in memory chips  
Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method...
7216284 Content addressable memory having reduced power consumption  
A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match...
7210084 Integrated system logic and ABIST data compression for an SRAM directory  
ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for...
7206987 Error detection and correction in a layered, 3-dimensional storage architecture  
A method and system for space-efficient error-control coding for encoding data into a 3-dimensional data-storage medium. The method and system enables the detection and correction of a bounded...
7206962 High reliability memory subsystem using data error correcting code symbol sliced command repowering  
A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into...
7206988 Error-correction memory architecture for testing production errors  
An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a...
7203886 Detecting and correcting corrupted memory cells in a memory  
A data storage comprises memory having a plurality of memory cells operative to retain data until read. A buffer cooperates, under the control of an address and buffer manager, with the memory to...
7203890 Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits  
A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit...
7203889 Error correction for memory  
A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the...
7191257 System and method for real-time processing of nondeterministic captured data events  
A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a...
7188299 Data-recording/reproduction apparatus and data-recording/reproduction method  
In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C 2 error correction for correcting an inter-sector error...
7181672 Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices  
A technique for coalesced Power Loss Recovery PLR status bits in an Error Correction Code ECC enabled flash memory.
7178087 Read-only record carrier with recordable area in subcode channel  
A method of providing a read-only record carrier on which user data can be recorded at predetermined recordable positions of subcode frames of a subcode channel after mastering of said record...
7171605 Check bit free error correction for sleep mode data retention  
A DRAM memory has a reduced refresh rate in a sleep mode to conserve power. Error Correction Codes (ECC) are used to correct errors that may arise due to the reduced refresh rate. ECC encoding...
7171606 Software download control system, apparatus and method  
A system and method for downloading software updates for receivers of broadcast content data distribution has multiple memories for storing the updated version of code as well as a backup copy of...
7167404 Method and device for testing configuration memory cells in programmable logic devices (PLDS)  
A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or...
7165206 SRAM-compatible memory for correcting invalid output data using parity and method of driving the same  
Disclosed herein is an SRAM-compatible memory for correcting invalid output data using parity and a method of driving the same. In the SRAM-compatible memory, input data and a parity value obtained...
7159165 Optical recording medium, data recording or reproducing apparatus and data recording or reproducing method used by the data recording or reproducing apparatus  
An optical recording medium, a data recording or reproducing apparatus, and a data recording or reproducing method used by the data recording or reproducing apparatus. In a method of recording data...
7159069 Simultaneous external read operation during internal programming in a flash memory device  
A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and...
7149948 Manufacturing test for a fault tolerant magnetoresistive solid-state storage device  
A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical defects. At manufacture, the...
7149949 Method for error correction decoding in a magnetoresistive solid-state storage device  
A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, a set of test cells in a test row are used to...
7149950 Assisted memory device for reading and writing single and multiple units of data  
A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The...
7143331 Error correction apparatus for performing consecutive reading of multiple code words  
An error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The device includes a memory access...
7134069 Method and apparatus for error detection and correction  
A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error...
7131050 Optimized read performance method using metadata to protect against drive anomaly errors in a storage array  
The present invention is an apparatus and method for protecting against drive anomaly errors while optimizing random read performance. Data block persistency is explicitly verified when a data...
7124347 Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture  
A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises providing serial data stream into the FPGA from an external source, loading data...
7120850 Low-cost methods and devices for the decoding of product cases  
A method of decoding product codes is disclosed, in which the symbols of each codeword may be placed in a table comprising n 2 rows and n 1 columns, such that the symbols constituting each row...
7117420 Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories  
An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a...
7117421 Transparent error correction code memory system and method  
The present invention provides flexible and efficient memory configuration that is capable of economically addressing both resource consumption and ECC concerns. A memory system facilitates...
7114118 System and method for providing adjustable read margins in a semiconductor memory  
A system and method for effectuating a self-timed clock (STC) loop for memory access operations wherein an Embedded Test and Repair (ETR) processor engine is utilized for optimizing an access...
7114117 Memory card and memory controller  
A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the...
7107507 Magnetoresistive solid-state storage device and data storage methods for use therewith  
A magnetoresistive solid-state storage device (MRAM device) uses storage cells 16 arranged in many arrays 10 to form a macro-array 2. For fast access times and to reduce exposure to physical...
7107508 Manufacturing test for a fault tolerant magnetoresistive solid-state storage device  
A fault-tolerant magnetoresistive solid-state storage device (MRAM) in use performs error correction coding and decoding of stored information, to tolerate physical failures. At manufacture, the...
Matches 151 - 200 out of 537 < 1 2 3 4 5 6 7 8 9 10 11 >