Matches 451 - 500 out of 540 < 1 2 3 4 5 6 7 8 9 10 11 >
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5479640 Memory access system including a memory controller with memory redrive circuitry  
A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory...
5459850 Flash solid state drive that emulates a disk drive and stores variable length and fixed lenth data blocks  
A flash solid state drive, having a flash solid state memory compatible with ATA/IDE Interface standards to be connected to a host for storing or retrieving sectors of data, where each sector...
5455939 Method and apparatus for error detection and correction of data transferred between a CPU and system memory  
A method and apparatus for detecting and correcting errors in data transferred between a CPU and system memory. System memory typically has a number of dynamic random access memory (DRAM) devices...
5446872 Method for error recovery in a non-synchronous control unit  
An error recovery process for a non-synchronous DASD control unit. A channel process within the control unit is able to operate on different fields from a device process within the control unit....
5430745 Prejudging current state in a decoder for coded signal processing channels  
Decoder for processing digital sample values corresponding to an incoming read signal representative of coded binary data. Functional expressions of digital sample values are precomputed for a...
5428630 System and method for verifying the integrity of data written to a memory  
A method and system for verifying the integrity of data written to a mass memory medium. A local memory is directed by local memory control logic to store a data block that is received from a host...
5410546 Apparatus and method for CRC computation over fixed length blocks containing variable length packets of data received out of order  
The present invention discloses a method and apparatus for computing CRC codes for fixed length page buffers of user data where the user data arrives from a transmission device in variable length...
5392288 Addressing technique for a fault tolerant block-structured storage device  
A fault tolerant addressing arrangement for a solid-state disk comprising partially defective memory devices is provided. The addressing technique increments both row and column addresses when...
5386549 Error recovery system for recovering errors that occur in control store in a computer system employing pipeline architecture  
An error recovery system used in a pipeline architecture type computer system for recovering from an error in a control word for an instruction without interrupting the sequence of processing...
5375231 Control memory error correcting apparatus  
A control memory error correcting apparatus includes a control memory, a microinstruction register, a control pattern generator, a control pattern storage register, and an operation inhibit signal...
5359468 Digital data storage tape formatter  
In a digital data storage audio tape system having a host device interface unit, a main data buffer manager, a main data buffer, a processor, a data separator, a tape drive unit, and a read/write...
5347648 Ensuring write ordering under writeback cache error conditions  
Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through...
5313464 Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols  
A symbol interleaving method for organizing data in a semiconductor memory such that fault tolerance of the memory is optimized when used in conjunction with a Reed-Solomon burst error correcting...
5313475 ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme  
An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers...
5313624 DRAM multiplexer  
The present invention provides a system for supporting one or more memory requestors (CPU's and I/O DMA) accessing a plurality of DRAM memory banks. The present invention is a multiplexer that...
5293383 Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order  
Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order. The test of a...
5291498 Error detecting method and apparatus for computer memory having multi-bit output memory circuits  
An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number...
5289377 Fault-tolerant solid-state flight data recorder  
A flight data recorder for reliable, high-speed storage of flight data employs a distributed, modular architecture in which an array of controller/memory modules is arranged in parallel...
5274646 Excessive error correction control  
A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor...
5274647 Elastic buffer with error detection using a hamming distance circuit  
An elastic buffer circuit uses codes having a predetermined number of bits and a Hamming distance of 1 when adjacent memory elements are designated. The codes contain a common code in which bits...
5267241 Error correction code dynamic range control system  
Disclosed is a dynamic range control circuit for determining when to allow an error correction circuit to correct data read from a sector of a disk data storage device. The circuit has two sets of...
5261084 Error judgment method  
In a method of judging a data memory access error in an information processing apparatus, the data memory access error flag is set in the process state register upon occurrence thereof, and an...
5255270 Method of assuring data write integrity on a data storage device  
A method for assuring data write integrity on a data storage device includes storing data in a temporary memory storage medium after receipt of the data and prior to writing the data to a storage...
RE34245 Two stage coding method  
Errors which arise in recording and reproducing data in a recording material are corrected with the use of an error correction code such as an RS (Reed-Solomon) code, and a two stage C 2 and C 1 ...
5206866 Bit error correcting circuit for a nonvolatile memory  
A bit correction circuit for a nonvolatile memory is connected between a non-volatile memory and a control circuit such as a microcomputer. The nonvolatile memory has a plurality of sets of memory...
RE34088 On-the-fly error correction  
On-the-fly error correction is provided by using the remainder from division of the encoded codeword by its generator polynomial to look up error values and locations in a memory. Alternatively,...
5144628 Microprogram controller in data processing apparatus  
A microprogram controller in a data processing apparatus includes a control storage device which has ECC bits and tri-state input/output pins, a first register for holding microprogram data read...
5127014 Dram on-chip error correction/detection  
Error detection or correction is provided on the same chip as DRAM memory. Because data and error correction bits need not travel on an external bus, error detection/correction can be conducted on...
5058116 Pipelined error checking and correction for cache memories  
A single error correction, double error detection function for cache memories does not affect the normal cache access time the addition of the ECC function. Check bits are provided for multiple...
5048022 Memory device with transfer of ECC signals on time division multiplexed bidirectional lines  
A memory for storing data in a computer system. Integrity of data transferred to or from a memory array is monitored by transferring two sets of EDC or ECC data corresponding to a longword of data...
5014273 Bad data algorithm  
An algorithm, and methodology for its application, useful in digital computer systems incorporating read-modify-write data storage systems to accurately identify rewritten data which has been...
4995041 Write back buffer with error correcting capabilities  
In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory...
4961193 Extended errors correcting device having single package error correcting and double package error detecting codes  
An apparatus and method for correcting data words from a memory is provided in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit...
4955023 Error correction control system for control memory  
An error correction control system for a control memory generates, when an error is detected in a microinstruction read out from a control memory to a microinstruction register, a first inhibit...
4942578 Buffer control method and apparatus  
A multiprocessor stores in a directory a validity bit for a line of a cache, history of updating and information relating to equality of data between processors. A portion of an error in the...
4920537 Method and apparatus for non-intrusive bit error rate testing  
This invention comprises a method and apparatus for determining the bit error rate (BER) between two points of a digital communications circuit carrying an arbitrary data stream. Block check codes...
4918695 Failure detection for partial write operations for memories  
A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any...
4901318 Address generating circuit  
An address generating circuit (13) generates a reading address for reading a buffer memory (16) so that so-called P and Q codes for a CD-ROM which have parameters i and j can be decoded. The...
4899342 Method and apparatus for operating multi-unit array of memories  
A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC)...
4887268 Error checking apparatus  
An error checking apparatus includes first and second switching circuits arranged at input and output ports of a data processing circuit for processing data constituted by a plurality of parallel...
4866719 System and method for performing error correction on still frame audio tape format video signals  
A system and method for performing error correction on an SFAT format video signal which has been encoded using an error correction code ECC2, and generating a video signal reconstructed from the...
4862462 Memory systems and related error detection and correction apparatus  
Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having single byte parallelism, each module having a...
4858235 Information storage apparatus  
In an information storage apparatus having an error-correcting code, wherein digital information and check symbols are stored in groups of codewords which are divided into blocks of equal size and...
4852100 Error detection and correction scheme for main storage unit  
The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second...
4827478 Data integrity checking with fault tolerance  
Fault tolerant apparatus for generating error correcting code and, simultaneous therewith, checking the correctness of the generation, for blocks of data with which the error correcting code is...
4788685 Apparatus for recording and reproducing data  
A recording and reproducing apparatus comprising a memory for storing input data to be recorded in units of a predetermined quantity, a first address control means for generating only sequential...
4780809 Apparatus for storing data with deferred uncorrectable error reporting  
The reporting of errors that are detected when data which contains an error is moved from a high speed buffer memory array to a main storage array is deferred so that the error checking and...
4775979 Error correction system  
An error correction system for a memory device of the type in which a data of plurality of bits is stored in a storage in the form of a coded word having as an end portion thereof a plurality of...
4761783 Apparatus and method for reporting occurrences of errors in signals stored in a data processor  
The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals;...
4727547 Method and apparatus for decoding  
Method and apparatus for transforming a first sequence of digital data and correction words having a first ordering thereof wherein blocks of data and correction words in the first ordering are...
Matches 451 - 500 out of 540 < 1 2 3 4 5 6 7 8 9 10 11 >