Matches 1 - 50 out of 68 1 2 >
Match Document Document Title
7613981 System and method for reducing power consumption in a low-density parity-check (LDPC) decoder  
A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module...
7590913 Method and apparatus of reporting memory bit correction  
Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of...
7565595 Convolutional interleaving and de-interleaving circuit and method thereof  
A convolutional interleaving and de-interleaving circuit and the method thereof are provided. The convolutional interleaving and de-interleaving circuit includes an initial address generator, a...
7539922 Bit failure detection circuits for testing integrated circuit memories  
A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality...
7536626 Power control using erasure techniques  
Techniques for performing erasure detection and power control for a transmission without error detection coding are described. For erasure detection, a transmitter transmits codewords via a...
7530004 Error correction apparatus using forward and reverse threshold functions  
An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the...
7512860 Communication system and receiving method  
A receiving apparatus in a communication system in which when a systematically encoded signal cannot be decoded correctly on a receiving side, the signal is retransmitted from a transmitting side....
7469014 Reduced bitstream candidate based receiver and received signal processing method  
A receiver comprises multiple receiving antennas configured to receive bitstreams transmitted from multiple transmission antennas; a bitstream candidate estimator configured to estimate a...
7461326 Information processing method capable of detecting redundant circuits and displaying redundant circuits in the circuit design process  
The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing...
7428688 Method of detecting two-dimensional codes  
A method of detecting two-dimensional codes using a plurality of light and dark data bits arranged two-dimensionally. The method includes detecting the code as a gray scale value image, splitting...
7406653 Anomaly detection based on directional data  
Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object. An anomaly detecting method includes: sequentially generating directional data...
7363553 System and method for adjusting soft decision thresholds in a soft-decision error correction system  
The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may...
7353170 Noise-adaptive decoding  
In one aspect the invention is a method for decoding. The method includes receiving encoded data and decoding the encoded data using a noise-adaptive decoder. The data may include first-order...
7320095 Optimization of the decision threshold for binary signals  
A threshold value is set in a decision circuit receiving a transmitted stream of binary symbols from a network link. The decision circuit uses the threshold value for detecting whether a 1 or a 0...
7313748 FEC decoder and method  
A method is described for FEC decoding a signal which has become affected by transmission errors, the original signal being transmitted together with parity data. The method comprises: receiving (...
7292655 Apparatus and method and decoding biphase signals  
A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital...
7272771 Noise and quality detector for use with turbo coded signals  
In one aspect this invention provides a method to operate a decoder, and a decoder that operates in accordance with the method. The method includes monitoring, during operation of the decoder on a...
7257760 Early decoding of a control channel in a wireless communication system  
Techniques are provided for performing early decoding of a message on a control channel in a wireless (e.g., GSM) communication system. In a GSM system, a message for a paging channel is...
7246303 Error detection and recovery of data in striped channels  
In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an...
7162241 Method for managing multicast group in mobile communication system  
A multicast service of a 3GPP Universal Mobile Telecommunications System (UMTS) is disclosed. By allowing an RNC to manage multicast group member information by multicast services on multicast...
7103825 Decoding error-correcting codes based on finite geometries  
A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a...
7095807 Method for decoding biphase signals  
A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d 1 )...
7051268 Method and apparatus for reducing power consumption of a decoder in a communication system  
A method and an apparatus for reducing power consumption of a decoder in a communication system are disclosed. In a communication system communicating a packet, the packet can be arranged among...
6982659 Method and apparatus for iterative decoding  
Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature...
6941506 Switching circuit for decoder  
A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome...
6910173 Word voter for redundant systems  
The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n...
6633615 Trellis transition-probability calculation with threshold normalization  
A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be...
6167552 Apparatus for convolutional self-doubly orthogonal encoding and decoding  
An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an...
6122767 Method and apparatus for noise reduction of cyclic signal by selecting majority logic state of corresponding portions of plural cycles  
An EDTV application utilizing a Synchronous Vector Processor (SVP) includes the operation whereby noise is reduced in the operation to demodulate the chroma signal. Initially, the NTSC composite...
6119937 Information reproduction system, information recording system and information recording medium utilizing an optically readable DOT code  
A threshold determination/binarization circuit and a recording medium for an information reproduction system, wherein the diameter of a reference dot detected by a reference dot diameter detection...
6094461 Data transmission  
A transmitter (20) having means (206, 207) to encode an input signal to form coded data, each element of said coded data having one of at least two discrete signal magnitude levels, the encoding...
6061820 Scheme for error control on ATM adaptation layer in ATM networks  
A scheme for error control on AAL in ATM networks capable of realizing a reliable communication with a high throughput and a low latency. On AAL, the segmented data are sequentially written into...
6044486 Method and device for majority vote optimization over wireless communication channels  
A method and device for error-correcting a plurality of bits transmitted over RF channels in a cellular communication system are provided. The present invention applies principles of majority...
5745506 Error correcting decoder  
An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if...
5745502 Error detection scheme for ARQ systems  
A method of error correction for an ARQ system allows decoding when an even number of flawed packets are received. Multiple flawed replications of a transmitted bit sequence are compared...
5726992 Circuit for and method of assessing an RDS signal  
A method of assessing the quality and/or existence of a biphase-modulated digital RDS signal in a radio signal broadcast by a radio transmitter and received by a radio receiver equipped for RDS, in...
5671256 Method for decoding a digital signal  
A received signal is sampled and a mean is calculated. A zero crossing sample is then located and used to locate a starting sample and the samples are read from that point forward, using sampling...
5559998 Clock synchronous serial information receiving apparatus receiving reliable information even when noise is present  
A clock synchronous information receiving apparatus comprising a control signal circuit 6 for receiving a communication clock 3 and outputting a control signal 8, a control signal generating...
5457702 Check bit code circuit for simultaneous single bit error correction and burst error detection  
A system for correcting a single bit error and detecting burst errors is provided. A check bit generator generates partition check bits and burst check bits based on a H-parity matrix data...
5357528 Depth-2 threshold logic circuits for logic and arithmetic functions  
The logical comparison and arithmetic addition functions are optimally constructed in depth-2 threshold logic circuits employing majority elements arranged into structures corresponding to sparse...
5103411 Electronic odometer wherein medium order digit data addresses locations which store high and low order digit data  
An electronic odometer is disclosed, in which, in order to provide higher reliability, integrated traveled distance data to be stored in a nonvolatile memory is divided into three portions, i.e.,...
5097486 Pipelined decision feedback decoder  
The decision feedback decoder of the invention receives sequentially sampled values of a signal waveform corresponding to data bits transmitted by a channel. A magnitude comparator compares the...
5003540 Error correction coding and decoding circuit for digitally coded information  
An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal...
4794600 Apparatus for error correction of digital image data by means of image redundancy  
Correction of PCM digital image data by encoding of the redundancy present in blocks of the data may be subject to faulty encoding for certain amounts of redundancy. This occurs at the boundaries...
4715037 Viterbi decoder comprising a majority circuit in producing a decoded signal  
In a Viterbi decoder for use in producing a decoded signal by correcting and decoding convolutional codes, a majority circuit (46) is connected to a path memory (45). At each of the time slots used...
4692709 Parallel input signal processor for low-level signal, high-noise environments  
In a parallel input signal processor, parallel input signals are processed using logic (selective weight) averaging. A multiple number of signal detectors are placed relatively close together at...
4675868 Error correction system for difference set cyclic code in a teletext system  
An error correction system for a difference set cyclic (272,190) code with 190 data bits and 82 test bits in a coded transmission teletext system which transmits character information on the...
4672612 Error correction system in a teletext system  
An error correction system for a difference set cyclic (272, 190) code with 190 data bits and 82 test bits in a packet which is transmitted on a vertical blanking interval of a television signal...
4654854 Method and apparatus for decoding threshold-decodable forward-error correcting codes  
Decoding performance of threshold-decodable forward-error-correcting codes is improved through the use of three methods. These methods employ measurements of received-digit reliability, and...
4630271 Error correction method and apparatus for data broadcasting system  
A random multi-error correcting code having a maximum length block in a packet, for instance a majority logic decodable (272, 190) shortened difference set cyclic code, is used for error correction...
Matches 1 - 50 out of 68 1 2 >