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RE40991 |
Fast cyclic redundancy check (CRC) generation
A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple...
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7613980 |
System for computing a CRC value by processing a data message a word at a time
A system for computing a CRC value includes at least one memory for storing a data message, a current CRC value, and a plurality of lookup tables. The data message includes a plurality of words,...
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7613256 |
Forward error correction in a distribution system
A multimedia distribution system is disclosed. The distribution system includes a transmitter unit that distributes content from a content provider to one or more wireless subscriber units. The...
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7606266 |
HDLC hardware accelerator
An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a...
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7600176 |
Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously
Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field...
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7590916 |
Cyclic redundancy checking value calculator
A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value...
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7571368 |
Digital content protection systems and methods
In an embodiment of the invention, an integrated circuit comprises an input module configured to receive a first data segment, an identifier module having a hard coded identifier, a processing...
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7543211 |
Toggle memory burst
A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to...
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7536631 |
Advanced communication apparatus and method for verified communication
A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word...
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7523305 |
Employing cyclic redundancy checks to provide data security
The security of data is enhanced by the use of cyclic redundancy checks. Data is encoded with one or more cyclic redundancy checks and then transmitted by a transmitter to a receiver. The receiver...
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7509564 |
High speed syndrome-based FEC encoder and system using same
A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing...
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RE40684 |
Fast cyclic redundancy check (CRC) generation
A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is...
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7458006 |
Methods for computing the CRC of a message from the incremental CRCs of composite sub-messages
A method of generating a CRC for a composite sub-message based on a CRC generating polynomial having at least two factors. The composite sub-message includes sub-message data and a number, n, of...
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7451382 |
Apparatus and method for generating (n,3) code and (n,4) code using simplex codes
An apparatus and method for generating a (n, 3) code and a (n, 4) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3) codeword with n code symbols, a...
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7395483 |
Method and apparatus for performing error-detection and error-correction
One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication...
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7383464 |
Non-inline transaction error correction
Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline...
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7318189 |
Parallel convolutional encoder
Methods and devices for encoding in parallel a set of data. bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being...
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7299399 |
Method and apparatus for parallelly processing data and error correction code in memory
A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first...
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7299398 |
Data generating method for forming desired CRC code
A method of generating a CRC code to determine a variable field value for equalizing a CRC value, which is calculated based on data including the variable field value of a variable field included...
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7278090 |
Correction parameter determination system
An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop...
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7254769 |
Encoding/decoding apparatus using low density parity check code
Disclosed is an encoding/decoding apparatus of a HARQ system using LDPC codes. A first LDPC code encoding apparatus encodes input information data and transmits the encoded data to the decoding...
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7225387 |
Multilevel parallel CRC generation and checking circuit
A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic,...
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7219293 |
High performance CRC calculation method and system with a matrix transformation strategy
A CRC calculation method and system for generating a CRC from a message is provided while improving the process time and simple to implement. A linear mapping matrix is used for the operation of...
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7194672 |
CRC verification apparatus with constant delay and method thereof
An apparatus and method for detecting errors in received data and transferring only error-free data in data communications are provided. In the cyclic redundancy check (CRC) verification apparatus...
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7181671 |
Parallelized CRC calculation method and system
A method and system for CRC calculation to an input message is provided while improving the process time and simple to implement. A linear mapping matrix corresponding to the LFSR to generate the...
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7178080 |
Hardware-efficient low density parity check code for digital communications
A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix...
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7149932 |
Serial communication device and method of carrying out serial communication
A serial communication device bridging between a parallel bus and a serial bus, includes (a) a check bit producer which applies an error correcting code to parallel data transmitted through the...
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7137057 |
Method and apparatus for performing error correction code (ECC) conversion
An Error Correcting Code (ECC) conversion facility includes a first interface for receiving input data protected in accordance with a first ECC, and first and second processing paths, each...
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7085983 |
Matrix operation processing device
An input data signal string I is temporarily stored in an input register, and is input to a parallel adder operating according to the instruction of a control unit. The control unit designates an...
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7055080 |
High code rate block coding/decoding method and apparatus
A block coding algorithm uses an original block group having n+1 original blocks of m-bit message, which a first original block of m-bit message is encoded as a reference block of n-bit codeword...
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7016658 |
Apparatus and method for transmitting/receiving data according to channel condition in a CDMA mobile communication system with antenna array
Disclosed is a method for providing first and second interleaved bit streams to a modulator in order to transmit the first and second interleaved bit streams through at least two antennas in a...
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6978416 |
Error correction with low latency for bus structures
Correction and location information are determined from a number of data vectors. The location information comprises values determined from subsets of the data vectors. Two or more of the subsets...
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6968491 |
Generating a check matrix for error correction
Generating a check matrix includes defining a set of column vectors. A matrix operable to have a plurality of entries is initiated. Each entry has a submatrix that includes a function of a subset...
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6961888 |
Methods and apparatus for encoding LDPC codes
Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow...
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6938197 |
CRC calculation system and method for a packet arriving on an n-byte wide bus
The present invention provides a cyclic redundancy check (CRC) calculation system for a packet arriving on an n-byte wide bus. In one embodiment, the system includes a bus-wide CRC subsystem...
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6934902 |
CRC encoding circuit, CRC encoding method, data sending device and data receiving device
A CRC encoding circuit for generating CRC bits in accordance with initial parallel data having remainder portion data in a last column of the initial parallel data. A first parallel encoding unit...
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6928608 |
Apparatus and method for accelerating cyclic redundancy check calculations
An apparatus and a method for accelerating Cyclic Redundancy Check (CRC) calculations. The apparatus includes a CRC circuit and an accelerator for accelerating the computation of the CRC code so...
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6912683 |
Method, apparatus, and product for use in generating CRC and other remainder based codes
A method, apparatus and product for use in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder...
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6851085 |
Apparatus and method for generating (n, 3) code and (n, 4) code using simplex codes
An apparatus and method for generating a (n, 3 ) code and a (n, 4 ) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3 ) codeword with n code symbols, a...
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6810501 |
Single cycle cyclic redundancy checker/generator
A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one...
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6772289 |
Methods and apparatus for managing cached CRC values in a storage controller
A CRC value cache architecture and methods of operation of same to reduce overhead processing associated with managing a CRC value cache memory. The invention first provides for transferring from...
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6763495 |
CRC code calculation circuit and CRC code calculation method
A CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data. In a CRC code calculation circuit 10 for calculating a CRC code from four-byte...
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6757860 |
Channel error protection implementable across network layers in a communication system
Channel error protection is provided for a source coded bit stream in a communication system by a combination of outer channel coding and inner channel coding implemented across different network...
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6745362 |
Method and device for error correction coding and corresponding decoding method and device
The invention concerns a method and a device for error correction coding associating with a data source series a coded data block, to be transmitted to at least one receiver comprising at least two...
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6732317 |
Apparatus and method for applying multiple CRC generators to CRC calculation
An apparatus and method for generating a cyclic redundancy code with multiple cyclic redundancy code circuits are disclosed. High throughput data protocols can work more robustly if accompanied by...
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6701478 |
System and method to generate a CRC (cyclic redundancy check) value using a plurality of CRC generators operating in parallel
The present invention relates to a system and method to generate a CRC (Cyclic Redundancy Check) value using a plurality of CRC generators operating in parallel. The system includes a switching...
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6684363 |
Method for detecting errors on parallel links
System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an...
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6560746 |
Parallel CRC generation circuit for generating a CRC code
The invention relates to a parallel CRC generation circuit comprising an input register means (I), an output register means (C), a number of XOR gates (XOR 1 -XOR N ) and a coupling means (CM) that...
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6560742 |
Parallel system and method for cyclic redundancy checking (CRC) generation
The present invention involves a method for generating a partial Cyclic Redundancy Checking (CRC) value of a first interval of data in a digital data stream. The method includes the step of loading...
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6530057 |
High speed generation and checking of cyclic redundancy check values
A parallel, recursive system for generating and checking a CRC value is disclosed, in which the feedback and forward terms are separated, and the forward terms are reduced. Forward logic, which...
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