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7395480 Test apparatus and test method  
The present invention provides a test apparatus comprising: a threshold voltage setting unit for setting threshold voltages of a logic device component connected to the signal propagation path; a...
7395475 Circuit and method for fuse disposing in a semiconductor memory device  
A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test...
7392444 Non-volatile memory evaluating method and non-volatile memory  
The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with...
7383477 Interface circuit for using a low voltage logic tester to test a high voltage IC  
The present invention provides an interface circuit for using a low voltage logic tester to test a high voltage IC. The interface circuit is between the high voltage IC and the low voltage logic...
7370247 Dynamic offset compensation based on false transitions  
A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment,...
7366966 System and method for varying test signal durations and assert times for testing memory devices  
A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in...
7363568 System and method for testing differential signal crossover using undersampling  
System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a device under test (DUT) and an automatic...
7363556 Testing apparatus and testing method  
A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory...
7315974 Method for detecting faults in electronic devices, based on quiescent current measurements  
The present invention is related to a method for testing a micro-electronic device, by applying a plurality of test vectors to said device, and measuring for each test vector, the quiescent supply...
7313747 Measuring microprocessor susceptibility to internal noise generation  
A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a...
7310760 Apparatus and method for initializing an integrated circuit device and activating a function of the device once an input power supply has reached a threshold voltage  
An apparatus for generating a function activation signal to activate a function in an integrated circuit device comprises a power-on circuit receiving a power input and initializing and generating...
7299380 Testing a receiver connected to a reference voltage signal  
A method and apparatus of testing a computer having a controller includes adjusting a reference voltage signal from a first level to a second level in response to an output from the controller. The...
7287205 Signal testing of integrated circuit chips  
A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC...
7281182 Method and circuit using boundary scan cells for design library analysis  
A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary...
7272767 Methods and apparatus for incorporating IDDQ testing into logic BIST  
Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG)...
7272763 Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices  
A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any...
7269524 Delay lock loop delay adjusting method and apparatus  
Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an...
7216271 Testing apparatus and a testing method  
A testing apparatus for performing a setup testing or a hold testing on a device under test (“DUT”) storing a given data signal according to a given clock signal is provided, wherein the...
7210085 Method and apparatus for test and repair of marginally functional SRAM cells  
A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of...
7203883 Integrated circuit  
An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input...
7185245 Test reading apparatus for memories  
Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the...
7174502 Synchronization error detection circuit  
Synchronization errors in a received pulse train are detected by detecting rising or falling transitions in the pulse train, generating numbers in a repeating cycle having a length corresponding to...
7165197 Apparatus and method of analyzing a magnetic random access memory  
In an apparatus for analyzing a magnetic random access memory (MRAM), and a method of analyzing an MRAM, the apparatus includes an MRAM mounting unit on which an MRAM is mounted, a magnetic field...
7139957 Automatic self test of an integrated circuit component via AC I/O loopback  
A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically...
7047471 Voltage margin testing of bladed servers  
A voltage margin testing blade is adapted for use in a bladed server having at least one internal adjustable power supply. The testing blade is further adapted to provide a control signal to the...
7039842 Measuring propagation delays of programmable logic devices  
Methods are described herein, for improving the accuracy of propagation delay measurements of programmable electronic devices in a production environment. In one method, a built-in self-test is...
7036063 Generalized fault model for defects and circuit marginalities  
A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact...
7024606 Method of generating test pattern for integrated circuit  
A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of...
7020595 Methods and apparatus for model based diagnostics  
Systems and methods for performing module-based diagnostics are described. In an exemplary embodiment, sensor values from an actual engine plant are input to an engine component quality estimator...
7007215 Test circuit capable of testing embedded memory with reliability  
A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock...
6981187 Test mode for a self-refreshed SRAM with DRAM memory cells  
A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the...
6980943 Flow for vector capture  
A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized...
6966022 System and method for determining integrated circuit logic speed  
An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal...
6944812 Mode entry circuit and method  
An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin.
6938194 Integrated circuit testing method and system  
A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a...
6934897 Scheduling the concurrent testing of multiple cores embedded in an integrated circuit  
Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and...
6910164 High-resistance contact detection test mode  
A method for testing a semiconductor memory device includes forcing the device into a logic state configuration that does not occur during normal operation of the device. The method may also...
6904551 Method and circuit for setup and hold detect pass-fail test mode  
A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the...
6889350 Method and apparatus for testing an I/O buffer  
A buffer circuit is provided having a driver device and an input device to receive a first set of signals and to produce a second set of signals. The driver device may receive the second set of...
6751763 Semiconductor device test method for optimizing test time  
A method of testing a semiconductor device begins by reading test information into a testing apparatus. The test information is used to determine whether to perform a normal test or a fuzzy test...
6745358 Enhanced fault coverage  
A tool and method for increasing fault coverage of an integrated circuit. The tool includes a key nodes detection device for matching key nodes to a fault grading report list of undetected nodes, a...
6717292 Method and structure for measurement of a multiple-power-source device during a test mode  
A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after...
6684356 Self-test ram using external synchronous clock  
A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a...
6643830 Fault portion locating method for semiconductor integrated circuit device  
To make it possible to locate a physically abnormal portion such as low-resistance short-circuiting between signal wirings or an open fault in a CMOS logic circuit without any design information,...
6604213 Method and apparatus for determining a minimum clock delay in a memory  
An apparatus and method for determining a minimum clock delay provided to sense amplifiers of a memory array. The method first determines a response time of the overall memory circuit by varying...
6598195 Sensor fault detection, isolation and accommodation  
A sensor in an engineering system can be tested to detect, isolate and accommodate faults. Initially, a modeled sensor value of each actual sensor value is generated as a function of a plurality of...
6598194 Test limits based on position  
A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output...
6564351 Circuit and method for testing an integrated circuit  
A test mode detector ( 12 a ) that places a multi-pin integrated circuit ( 10 ) in test mode. The test mode detector ( 12 a ) comprises a pulse detector ( 25 ) that receives a control signal. The...
6519108 Method and apparatus for testing MR head instability using a criterion that removes normal head fluctuation from consideration  
A method and apparatus for detecting disk drive head instability. Normal head fluctuation is removed from the criterion used to detect whether a head is unstable. The present invention accumulates...
6513136 Communications receiver arrangement  
A receiver in a digital communications system, in which the digital data occupy a number of levels, equalises the erroneous-count rates for the various data levels by deriving the count rates for...
Matches 1 - 50 out of 182 1 2 3 4 >