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7624319 Performance monitoring system  
A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation...
7617431 Method and apparatus for analyzing delay defect  
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
7610539 Method and apparatus for testing logic circuit designs  
Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is...
7607061 Shrink test mode to identify Nth order speed paths  
In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock...
7603600 Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereon a timing failure diagnosing program for an integrated circuit, and computer readable recording medium recorded thereon a timing failure remedying program for an integrated circuit  
A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core...
7587650 Clock jitter detector  
A detector to detect the magnitude of the jitter that may occur in a first clock signal and a second clock signal and to generate an alarm signal if the magnitude of the jitter exceeds the...
7584393 Scan test circuit and method of arranging the same  
Replaced cell CELL 1 is composed of clock buffer circuit CB 1 and flip-flop circuit FF 1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB 1 a -CB 1 d are...
7574635 Circuit for and method of testing a memory device  
Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a...
7574633 Test apparatus, adjustment method and recording medium  
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
7571363 Parametric measurement of high-speed I/O systems  
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
7568138 Method to prevent firmware defects from disturbing logic clocks to improve system reliability  
A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation...
7558998 Semiconductor apparatus and clock generation unit  
A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input...
7549101 Clock transferring apparatus, and testing apparatus  
There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of...
7549092 Output controller with test unit  
There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an...
7546497 Semiconductor memory device and data write and read method thereof  
A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a...
7543210 Semiconductor device and test system thereof  
A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating...
7543209 Characterizing jitter sensitivity of a serializer/deserializer circuit  
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
7533317 Serializer/deserializer circuit for jitter sensitivity characterization  
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
7526704 Testing system and method allowing adjustment of signal transmit timing  
A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which...
7519880 Burn-in using system-level test hardware  
A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a...
7516385 Test semiconductor device in full frequency with half frequency tester  
An integrated circuit comprises a double frequency clock generator and a double input generator to test semiconductor devices at frill frequency using a half frequency tester. A clock generator...
7516384 Semiconductor memory testing device and test method using the same  
A test device for a semiconductor memory device includes a clock frequency multiplier, a data input buffer, a test data generator and a data output buffer. The clock frequency multiplier multiplies...
7516374 Testing circuit and related method of injecting a time jitter  
A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the...
7512858 Method and system for per-pin clock synthesis of an electronic device under test  
A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and...
7512848 Clock and data recovery circuit having operating parameter compensation circuitry  
A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are...
7509545 Method and system for testing memory modules  
A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two...
7506222 System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling  
A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the...
7502974 Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets  
In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is...
7496813 Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin  
An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared...
7496803 Method and apparatus for testing an integrated device's input/output (I/O)  
A plurality of timing diagrams and different versions of circuits to test an integrated device in a test mode of operation. The invention allows for pulling in a strobe and eliminating the need for...
7492793 Method for controlling asynchronous clock domains to perform synchronous operations  
A method for controlling asynchronous clock domains to perform synchronous operations is provided. With the method, when a synchronous operation is to be performed on a chip, the latches of the...
7487423 Decoding method, medium, and apparatus  
A decoding method, medium, and apparatus capable of preventing error propagation and implementing parallel processing. A decoding method includes comparing encoding information with decoding...
7484148 Interface error monitor system and method  
An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with...
7484135 Semiconductor device having a mode of functional test  
A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a...
7480839 Qualified anomaly detection  
A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start...
7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device  
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
7475310 Signal output circuit, and test apparatus  
A signal output circuit for outputting an output signal in accordance with a predetermined system timing is provided. The signal output circuit includes a shift register that delays an input signal...
7472329 Shift register, data line driving circuit, scanning line driving circuit, electro-optical device, and electronic apparatus  
To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation...
7461317 System and method for aligning a quadrature encoder and establishing a decoder processing speed  
A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a...
7461316 Multi-strobe generation apparatus, test apparatus and adjustment method  
A multi-strobe generation apparatus for generating a multi-strobe has a plurality of strobes. The multi-strobe generation apparatus includes a shift clock generating section which outputs a shift...
7454681 Automatic test system with synchronized instruments  
A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or...
7444576 Target value search circuit, taget value search method, and semiconductor test device using the same  
In a tentative target value calculation section 28 , a predetermined value is subtracted from (or added to) a target value Exp to calculate a tentative target value ExpB. In a binary search...
7444570 Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test  
A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit,...
7444560 Test clocking scheme  
A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates...
7437629 Method for checking the refresh function of an information memory  
A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information...
7434121 Integrated memory device and method for its testing and manufacture  
An integrated memory device includes an array of memory cells for storing data, a memory cell selector operationally connected to the array for selecting at least one memory cell of the array, a...
7434114 Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same  
A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to...
7424656 Clocking methodology for at-speed testing of scan circuits with synchronous clocks  
A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in...
7420400 Method and apparatus for on-chip duty cycle measurement  
The disclosed methodology and apparatus measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit located “on-chip”, namely on...
7412640 Self-synchronizing pseudorandom bit sequence checker  
Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in...
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