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7404115 Self-synchronising bit error analyser and circuit  
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus...
7401306 Apparatus and method for verification support, and computer product  
A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus...
7383481 Method and apparatus for testing a functional circuit at speed  
An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7379860 Method for integrating event-related information and trace information  
A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is...
7373575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
7373571 Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques  
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test...
7363563 Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers  
Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a...
7363556 Testing apparatus and testing method  
A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory...
7360139 Semiconductor component, arrangement and method for characterizing a tester for semiconductor components  
A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path between tester and semiconductor...
7359367 Device for preventing erroneous synchronization in wireless communication apparatus  
An erroneous synchronization preventing device includes a pattern detector detecting a sync pattern from received data with a broader sync window to output a sync detection notice and a sync...
7358715 Semiconductor integrated circuit  
By mounting, on a semiconductor integrated circuit, a clock stability waiting circuit 4 for deciding whether a clock signal generated by a high speed clock generating circuit 2 is stable or...
7349510 Apparatus for data recovery in a synchronous chip-to-chip system  
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling...
7346822 Integrated circuit  
An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to...
7340629 Method and system for application-based normalization of processor clocks in a multiprocessor environment  
A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first...
7332926 Semiconductor test apparatus  
Good device PASS/FAIL determination is realized by measuring timings of a cross point of differential clock signals CLK and a data signal DATA output from a DUT, and obtaining a relative phase...
7330994 Clock control of a multiple clock domain data processor  
A processor clock control device operable to control a plurality of clock signals output to a processor, said processor comprising a plurality of domains each clocked by a respective one of said...
7330993 Slew rate control mechanism  
According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the...
7330045 Semiconductor test apparatus  
Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization...
7320098 Semiconductor integrated circuit device having scan flip-flop circuit  
A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating...
7310752 System and method for on-board timing margin testing of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
7308381 Timing verification method for semiconductor integrated circuit  
Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew...
7305604 Determining edge relationship between clock signals  
First and second clock signals are provided to first and second sequential circuits, where the first and second clock signals are inversely coupled to logic high and low levels for clocking of the...
7305598 Test clock generation for higher-speed testing of a semiconductor device  
Embodiments for generating a higher frequency test clock signal for a semiconductor device are disclosed. In an example embodiment, a clock generator may be coupled to a clock input. A test clock...
7299392 Semiconductor integrated circuit device and method of design of semiconductor integrated circuit device  
A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device...
7296203 Test apparatus, program and recording medium  
There is provided a test apparatus for testing a device-under-test, having a master channel provided in correspondence to one of output pins of the device-under-test to sample an output signal of...
7293214 Testable design methodology for clock domain crossing  
A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals...
7289946 Methodology for verifying multi-cycle and clock-domain-crossing logic using random flip-flop delays  
A design tool inserts randomized delays into synchronizers for signals crossing from one clock domain to another. Rather than having a wide range of random delays to select from, each...
7278069 Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration  
A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data...
7275197 Testing apparatus  
A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes an operation order...
7275194 Clock duty cycle based access timer combined with standard stage clocked output register  
An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the...
7269524 Delay lock loop delay adjusting method and apparatus  
Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an...
7266744 Application specific integrated circuit with internal testing  
Application specific integrated circuits (ASICs) and methods are provided which allow for internal testing of an ASIC. One ASIC embodiment includes a processor on the ASIC. A memory is coupled to...
7266739 Systems and methods associated with test equipment  
The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a test system...
7263643 Test apparatus and testing method  
A test apparatus for testing electronic devices is provided which includes a plurality of signal sources to supply an output signal to test electronic devices according to an input signal, a loop...
7260653 Method and device for the synchronization between two networks  
The present invention relates to a method of synchronization between communication networks exchanging information by frame of informations, each communication network having clock and the number...
7257756 Digital frequency synthesis clocked circuits  
Embodiments of the invention may include a reference input port to receive a reference clock, the reference clock being based on a bypass clock, a feedback input port to receive a feedback clock...
7251765 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit  
A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a...
7251764 Serializer/deserializer circuit for jitter sensitivity characterization  
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
7249290 Deskew circuit and disk array control device using the deskew circuit, and deskew method  
A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern...
7246286 Testing methods and chips for preventing asnchronous sampling errors  
Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a...
7240269 Timing generator and semiconductor testing device  
A timing generator f or a semiconductor test device reduces pattern-dependent jitters and timing errors of timing pulse signals. In the timing generator, a delaying circuit (variable delaying...
7237167 Testing apparatus  
A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes a first and a second...
7234094 Automaton synchronization during system verification  
A method and apparatus for synchronizing a non-deterministic automaton being processed on a computing device during dynamic verification of a system or device under test, is described herein.
7234088 Method and apparatus for generating signal transitions used for testing an electronic device  
The present invention is directed to an improved method, system and apparatus for self-testing an electronic device. A scan latch used in a multi-cycle bus is uniquely operated to generate signal...
7231573 Delay management system  
A delay management system in a computer system includes a delay manager and a first storage element that stores a delay time. The delay manager is configured to receive a series of delay values and...
7225379 Circuit and method for testing semiconductor device  
A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a...
7222275 Test apparatus and writing control circuit  
A writing control circuit for writing command data supplied from a plurality of host computers onto any of a plurality of register sections, the writing control circuit includes a plurality of...
7216279 Testing with high speed pulse generator  
An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated...
7216271 Testing apparatus and a testing method  
A testing apparatus for performing a setup testing or a hold testing on a device under test (“DUT”) storing a given data signal according to a given clock signal is provided, wherein the...
Matches 1 - 50 out of 307 1 2 3 4 5 6 7 >