Matches 151 - 200 out of 311 < 1 2 3 4 5 6 7 >
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6477675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data...
6470468 Test pattern generator, propagation path disconnecting method, and delay fault detecting method  
A test pattern generator for automatically generating a test pattern for detecting a stack fault of a large scale integrated circuit an LSI with a tester includes a loop/path disconnecting section...
6470467 Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester  
A driver circuit applies a write data whose level is inverted for every write cycle to a selected memory cell in accordance with a write data held by a latch circuit when a writing operation in a...
6463337 Railroad vital signal output module with cryptographic safe drive  
A railroad vital signal output module provides a predetermined output signal in response to a certain module input only under conditions that insure vitality of the output signal. The module...
6449742 Test and characterization of source synchronous AC timing specifications by trace length modulation of accurately controlled interconnect topology of the test unit interface  
An apparatus that can determine whether a Tva parameter and a Tvb parameter of a device under test (DUT) complies with a design specification where the device under test is coupled to a secondary...
6449738 Apparatus for bus frequency independent wrap I/O testing and method therefor  
A bus-clock-speed-independent apparatus and method of wrap input/output (I/O) testing of an I/O interface is provided. Launch data is launched in response to a launch clock. A capture clock is...
6430720 Functional testing method and circuit including means for implementing said method  
The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern...
6421801 Testing IO timing in a delay locked system using separate transmit and receive loops  
A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode...
6418547 Internal guardband for semiconductor testing  
An internal guardband for use in semiconductor testing is disclosed. One aspect of the invention is a semiconductor circuit having two paths. The first path is a standard path, used for normal...
6418545 System and method to reduce scan test pins on an integrated circuit  
The present invention is a system and method that permits appropriate scan testing of internal components of an integrated circuit while reducing the number of external pins required to perform the...
6405336 Device and method for testing a semiconductor  
A method for generating a test pattern used for testing, by an LSI tester, a semiconductor integrated circuit having external terminals and sequential unitary circuits, comprising the steps of:...
6404805 Bit error measuring device for modem device and bit error measuring method for the same  
A bit error measuring device for modem device, comprises; a bit error measuring unit for measuring a bit error in an input signal from the modem device, a clock controlling unit for controlling an...
6401227 Timing fault diagnosis method and apparatus  
A timing fault diagnosis method diagnoses a timing fault of an integrated circuit chip having a logic circuit formed therein. The timing fault diagnosis method includes steps of (a) obtaining fail...
6374392 Semiconductor test system  
A semiconductor test system is capable of generating timing edges in the same direction having a time interval smaller than a reference clock cycle. The semiconductor test system includes a...
6353906 Testing synchronization circuitry using digital simulation  
To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time...
6349399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same  
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the...
6317372 Semiconductor memory device equipped with serial/parallel conversion circuitry for testing memory cells  
An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An...
6260167 Apparatus and method for deterministic receiver testing  
A physical layer (PHY) device in an Ethernet type LAN is configured to permit ease of testing of the PHY device's logic. The PHY device comprises a PHY receiver, a start frame delimiter detector...
6256240 Semiconductor memory circuit  
A semiconductor memory circuit includes a circuit which generates a test mode entry signal which enables a test mode directed to evaluating the semiconductor memory circuit. The circuit generates...
6246618 Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof  
A semiconductor integrated circuit comprises many RAMs, a supplementary RAM, and test/repair control logic which detects a defective RAM out of the multiple RAMs. If a defective RAM is detected,...
6237119 Method and system for making internal states of an integrated circuit visible during normal operation without the use of dedicated I/O pins  
A system includes a first integrated circuit and a second integrated circuit coupled by at least one signal line. The first integrated circuit outputs on the signal line an interleaved output...
6223318 IC tester having region in which various test conditions are stored  
An IC tester includes a test pattern storage circuit that stores a test pattern, a delay amount storage table that stores a test condition, an offset address generation circuit that divides the...
6223317 Bit synchronizers and methods of synchronizing and calculating error  
The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes...
6201838 Mobile communication system  
A mobile communication system includes a demodulator demodulating an interleaved data signal and outputting a demodulated data. A deinterleaver data array receives and deinterleaves the demodulated...
6199185 Test method for high speed semiconductor devices using a clock modulation technique  
A test method for testing a semiconductor device includes providing a tester which generates a plurality of general clock signals and which has a minimum test cycle time greater than an operational...
6195772 Electronic circuit testing methods and apparatus  
An electronic circuit tester (e.g., for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system...
6175914 Processor including a combined parallel debug and trace port and a serial port  
A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace...
6175529 Semiconductor integrated circuit device and method for manufacturing the same  
For enabling the self-test of a memory with a small number of input and output pins, and the burn-in tests of a memory and a logic to be carried out simultaneously in a memory/logic circuit mixed...
6170069 Bit error measuring device for modem device and bit error measuring method for the same  
A bit error measuring device for modem device, comprises; a control code detecting unit for detecting a flow control code set in an input signal from the modem device, and for masking the flow...
6125465 Isolation/removal of faults during LBIST testing  
A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches...
6105157 Salphasic timing calibration system for an integrated circuit tester  
An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The...
6094737 Path test signal generator and checker for use in a digital transmission system using a higher order virtual container VC-4-Xc in STM-N frames  
A path test signal generator and checker which can achieve a path test by effectively generating a path test signal in a system handling synchronous transport modules STM-Ns with an order higher...
6088824 Test pattern generating apparatus, communication device and simulator  
A test pattern generating apparatus generates a test pattern for evaluating whether or not source data and a bit synchronous clock signal SCK are transmitted normally through a bus connecting a...
6081913 Method for ensuring mutual exclusivity of selected signals during application of test patterns  
A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive...
6073261 Circuit for evaluating signal timing  
The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the...
6049900 Automatic parallel electronic component testing method and equipment  
A method of automatically testing electronic components in parallel, identical pins (i; i+1) of said components interchanging test signals with at least one common test circuit (20; 20') which...
6032282 Timing edge forming circuit for IC test system  
A timing edge forming circuit includes a pattern generator for generating address data, a rate signal and pattern data, a first logic delay circuit for generating first delay time data by the...
6009546 Algorithmic pattern generator  
An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction...
5996099 Method and apparatus for automatically testing electronic components in parallel utilizing different timing signals for each electronic component  
Apparatus for selectively testing, in parallel, identical pins of a plurality of electronic components is provided. The apparatus enables testing of selective pins of selective electronic...
5983382 Automatic retransmission query (ARQ) with inner code for generating multiple provisional decodings of a data packet  
The invention discloses techniques for providing automatic retransmission query (ARQ) functions in a communication system. A transmitter in the system applies an input data packet to a first...
5964894 IC test equipment, measurement method in the IC test equipment, and storage medium of the same  
An IC test equipment corrects the timing data for generating the strobe signal by each of the paths corresponding to a plurality of the devices under test measured in parallel and achieves an...
5960009 Built in shelf test method and apparatus for booth multipliers  
A Built-In Self Test (BIST) method and apparatus for Booth multipliers, wherein a fixed-size (8-bit) binary counter is used along with accumulator-based output data compaction. The fault model...
5946362 Apparatus for detecting clock failure for use in a synchronous transmission system  
An apparatus for use in a synchronous transmission system, for detecting a failure of a clock signal, which comprises: a reference clock generator for generating a reference clock signal (RCS) in...
5938785 Automatically determining test patterns for a netlist having multiple clocks and sequential circuits  
A method and computer system for automatically determining test patterns for a netlist having multiple clocks and sequential circuits. The invention utilizes a static model of a sequential circuit...
5938780 Method for capturing digital data in an automatic test system  
A method for operating automatic test equipment for capturing digital data produced by a semiconductor device under test, whereby the digital data is repetitively sampled to produce a series of...
5920490 Integrated circuit test stimulus verification and vector extraction system  
A logic simulation monitoring system to verify a test stimulus set and generate a test vector set for use on an Automatic Test Equipment (ATE) device during manufacturing tests. The simulation...
5918198 Generating pulses in analog channel of ATE tester  
A method simulating the filtering of a current pulse in a series of pulses. The method includes receiving a series of n+1 consecutive pulse addresses, including a pulse address for the current...
5878055 Method and apparatus for verifying a single phase clocking system including testing for latch early mode  
A method and apparatus are provided for efficiently verifying an on-chip single phase clocking system including testing for latch early mode. A variable delay clock circuit is provided for...
5875153 Internal/external clock option for built-in self test  
An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150)...
5856986 Synchronization field pattern selection  
A detection device for detecting a pattern and determining valid patterns by a series of tests. These tests include rejecting patterns based on minimum Hamming distance, spectral energies that are...
Matches 151 - 200 out of 311 < 1 2 3 4 5 6 7 >