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7617425 Method for at-speed testing of memory interface using scan  
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
7603604 Test apparatus and electronic device  
A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence...
7584394 System and method for pseudo-random test pattern memory allocation for processor design verification and validation  
A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described...
7577885 Semiconductor integrated circuit, design support software system and automatic test pattern generation system  
A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first...
7543199 Test device  
A test device that can improve test reliability is provided. In the test device, an error detecting unit detects an error of inputted test signals to generate an error flag, a normal test unit...
7533310 Semiconductor memory test device and method thereof  
A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory...
7426668 Performing memory built-in-self-test (MBIST)  
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more...
7421629 Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure  
The invention relates to a semi-conductor component test procedure, and a semiconductor component test device ( 10 b ), which comprise: a device ( 43 ) for generating pseudo-random address...
7415536 Address query response method, program, and apparatus, and address notification method, program, and apparatus  
Upon reception of a query about the address of a server from a client, a DNS server sends a query about the address of that server to an external DNS server. The DNS server checks based on the...
7337378 Semiconductor integrated circuit and burn-in test method thereof  
To provide a semiconductor integrated circuit that includes a flash EEPROM on which an efficient burn-in test can be carried out and a burn-in test method thereof. By changing the level of a...
7299388 Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer  
A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a...
7283409 Data monitoring for single event upset in a programmable logic device  
Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable...
7249296 Semiconductor integrated circuit  
An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and...
7114112 Method, system, and program for simulating Input/Output (I/O) requests to test a system  
Provided are a method, system, and program for simulating I/O requests to test a system coupled to an adaptor having a port used for transmitting and receiving I/O requests to the system. A user...
7072131 Water marking in a data interval gap  
A storage device in which file data is divided into multiple blocks for storage on a recording medium. The storage device includes an additional data storing section for storing additional data to...
6971055 Method for verifying the accuracy of bit-map memory test programs  
A method for verifying the accuracy of bit-map memory test programs is disclosed, which employs a Focused Ion Beam (FIB) apparatus to make or break connections on one or more word lines or bit...
6964000 Semiconductor integrated circuit device having a test circuit of a random access memory  
32 pseudo-random numbers respectively indicated by 5 bits are successively generated in a test address generating unit, a serial output signal denoting one pair of pseudo-random numbers of 10 bits...
6957373 Address generator for generating addresses for testing a circuit  
An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base...
6915469 High speed vector access method from pattern memory for test systems  
A method for applying test vectors to a device under test (DUT) at a speed of the DUT is disclosed. A pattern memory is re-organized into m modules, where m is a DUT/pattern memory speed ratio....
6893973 Method of etching silicon nitride film and method of producing semiconductor device  
Provided is a method of etching a silicon nitride film, which comprises subjecting the silicon nitride film located on copper to dry etching using a mixture of fluorocarbon gas and an inert gas as...
6865707 Test data generator  
Test data generator for generating test data patterns for the testing of a circuit having a frequency multiplication circuit, which increases a low clock frequency of an input clock signal received...
6836868 High-speed algorithmic pattern generator  
An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several...
6826111 On chip scrambling  
A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of...
6769084 Built-in self test circuit employing a linear feedback shift register  
A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test...
6760872 Configurable and memory architecture independent memory built-in self test  
A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an...
6721915 Memory testing method  
In the case where the internal configuration is different in each memory (in the case where the correspondence information between the program address designated by the testing program and the...
6687855 Apparatus and method for storing information during a test program  
An apparatus for automatically accumulating and storing information has a destination memory and an indexing circuit. The indexing circuit has an input port, a selector having a selector output, a...
6671845 Packet-based device test system  
A packet generator that increases the output speed of column and row addresses and data provided by a semiconductor device test system. The packet generator receives column and row addresses and...
6647526 Modular/re-configurable test platform  
A system and method is provided for testing industrial control modules. Input and output stimulus signals, communication lines, measurement device lines and relay contacts are provided at a tester...
6560731 Method for checking the functioning of memory cells of an integrated semiconductor memory  
In a method for checking the functioning of memory cells of an integrated semiconductor memory, a first group of the memory cells is tested. The test results, separately for each tested memory...
6523135 Built-in self-test circuit for a memory device  
A built-in self-test (BIST) circuit in a DRAM has a test mode controller including a mode counter for selecting based on the count thereof one of a plurality of test modes, and a plurality of test...
6502216 Memory device testing apparatus  
A memory device testing apparatus for testing a memory device ( 62 ) has a failure analysis memory unit ( 80 ) which includes: a data storing memory ( 12 ), in which fail data ( 26 ) output from a...
6492923 Test system and testing method using memory tester  
A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the...
6477676 Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips  
An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective...
6412087 Pattern data transfer circuit  
A pattern data transfer circuit capable of decreasing the number of transfer of pattern data and of shortening the entire transfer time as a whole. A chip selector circuit generates pin group data...
6381715 System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module  
A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are...
6338154 Apparatus and method for generating addresses in a built-in self memory testing circuit  
A memory address generating apparatus and method of a dynamic memory testing circuit for generating addresses for testing a dynamic memory which uses all the available addresses of the dynamic...
6249533 Pattern generator  
There is provided a pattern generator which is capable of utilizing memory blocks connected to unused pins of a DUT. A pattern address from a vector generation control 1 and a control signal from a...
6201838 Mobile communication system  
A mobile communication system includes a demodulator demodulating an interleaved data signal and outputting a demodulated data. A deinterleaver data array receives and deinterleaves the demodulated...
6189119 Semiconductor memory device having test mode  
A counter is provided in an SRAM using a CSP (Chip Scale Package). The counter includes n+1 stages of flipflops, counts the number of pulses of an address clock signal when a test signal attains...
6158037 Memory tester  
There is provided a memory testing apparatus for testing an IC memory having a failure relief line or lines, which is constructed to sufficiently serve to test using a failure analysis memory...
6154865 Instruction processing pattern generator controlling an integrated circuit tester  
A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR)...
6148426 Apparatus and method for generating addresses in a SRAM built-in self test circuit using a single-direction counter  
A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses...
6094738 Test pattern generation apparatus and method for SDRAM  
A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for a synchronous dynamic RAM (SDRAM) by having a specific wrap conversion circuit or an address...
6061816 Timing generator for testing semiconductor storage devices  
A timing generator operates in response to test cycles to generate test pulses for testing of semiconductor storage devices. For example, the timing generator is designed to generate two test...
6061815 Programming utility register to generate addresses in algorithmic pattern generator  
A algorithmic pattern generator (APG) in a memory tester having a programmable first ALU generating an first value on a first output data path; a programmable Z ALU generating a Z value on an Z...
6061813 Memory test set  
In a memory testing apparatus capable of testing both memories of a parallel input/parallel output type and a serial input/serial output type, in case of testing the serial input/serial output type...
6032281 Test pattern generator for memories having a block write function  
A test pattern generator for performing a block write function testing at high speed. The test pattern generator includes a data register which takes in data signal from a data generator by a first...
6009546 Algorithmic pattern generator  
An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction...
6006349 High speed pattern generating method and high speed pattern generator using the method  
A high speed pattern generating method by which a pattern signal having a speed higher than conventional speed can be generated using a sequence control part operating at a speed equivalent to a...
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