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7627843 Dynamically interleaving randomly generated test-cases for functional verification  
The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct...
7627799 Panel driving circuit that generates panel test pattern and panel test method thereof  
A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern...
7627790 Apparatus for jitter testing an IC  
An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a...
7624318 Method and apparatus for automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number  
A computer implemented method, a data processing system, and a computer usable program code for automatically identifying multiple combinations of operational and non-operational components with a...
7620861 Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels  
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
7617425 Method for at-speed testing of memory interface using scan  
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
7617426 Verification method and apparatus  
A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc;...
7613974 Fault detection method and apparatus  
This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a...
7610538 Test apparatus and performance board for diagnosis  
A test apparatus being capable of replacing a test module with the other kind of test module that tests device under tests by using the test module is provided. The test apparatus includes a...
7607056 Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices  
Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation...
7603595 Memory test circuit and method  
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and...
7603598 Semiconductor device for testing semiconductor process and method thereof  
A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing...
7596731 Test time reduction algorithm  
Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of...
7590911 Apparatus and method for testing and debugging an integrated circuit  
An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the...
7590912 Using a chip as a simulation engine  
The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and...
7587645 Input circuit of semiconductor memory device and test system having the same  
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
7587655 Method of transferring signals between a memory device and a memory controller  
Method and apparatus for communication (e.g., transmitting and/or receiving) command, address and data signals from a memory device to a memory controller or vice versa. The data signals are...
7584395 Systems, methods and apparatus for synthesizing state events for a test data stream  
In one embodiment, a method of has the steps of A) accessing a stream of test data comprising 1) a number of state events and 2) a number of data events interspersed with the ones of the state...
7577540 Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards  
A test system for a circuit board , wherein the circuit board has a plurality of cores such that at least one of the plurality of cores is adapted to use a test protocol independent of a...
7574644 Functional pattern logic diagnostic method  
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
7568141 Method and apparatus for testing embedded cores  
The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the...
7562276 Apparatus and method for testing and debugging an integrated circuit  
An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and...
7559001 Method and apparatus for executing commands and generation of automation scripts and test cases  
A command execution terminal includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses and maintaining a...
7559003 Semiconductor memory test apparatus  
A semiconductor memory test apparatus has a log data generating unit for generating log data indicating a test result of a device under test based on output data from the device under test...
7555690 Device for and method of coupling test signals to a device under test  
Various embodiments of the present invention relate to a device for testing an integrated circuit. According to one embodiment, the device comprises a first connector coupled to receive a device...
7552370 Application specific distributed test engine architecture system and method  
An Application Specific Distributed Test Engine (ASDTE) that provides an optimized set of test resources for a given application. The test engine resources, configuration, functionality, and even...
7552040 Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects  
A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times....
7549100 Dynamic verification traversal strategies  
A method of implementing a traversal strategy as part of a dynamic verification can include initializing a non-deterministic automaton (NDA) traversal mechanism that has (1) a strategy push-down...
7548828 Automatic test equipment platform architecture using parallel user computers  
The present invention provides a system of testing semiconductor devices. The system comprises a central host computer, an array of user computers (the array), and a HU (Host-User) network as the...
7546507 Method and apparatus for debugging semiconductor devices  
A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies...
7543200 Method and system for scheduling tests in a parallel test system  
An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two...
7539913 Systems and methods for chip testing  
Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage...
7536615 Logic analyzer systems and methods for programmable logic devices  
A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for...
7533310 Semiconductor memory test device and method thereof  
A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory...
7530000 Early detection of storage device degradation  
An apparatus operable with a host and a data storage component for detecting a storage device susceptible to failure under I/O workload is provided. The apparatus includes a selector component for...
7526701 Method and apparatus for measuring group delay of a device under test  
A method of measuring group delay of a device under test is provided. The method includes the steps of providing an analog input signal with a predetermined period to the device under test to...
7526699 Method for creating a built-in self test (BIST) table for monitoring a monolayer deposition (MLD) system  
A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber, calculating dynamic...
7526693 Initial decision-point circuit operation mode  
A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode....
7523366 Storage efficient memory system with integrated BIST function  
A method and system conduct built-in-self-test (BIST) in a circuit under test. After allocating at least one memory segment with a predetermined size in at least one memory module as a test result...
7523367 Method and apparatus to verify non-deterministic results in an efficient random manner  
The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a...
7519885 Monitoring a monolayer deposition (MLD) system using a built-in self test (BIST) table  
A method of monitoring a processing system in real-time using low-pressure based modeling techniques that include processing one or more of wafers in a processing chamber; determining a measured...
7519883 Method of configuring a system and system therefor  
A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan...
7516374 Testing circuit and related method of injecting a time jitter  
A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the...
7516373 Method for testing the error ratio of a device using a preliminary probability  
A method for testing the (Bit) Error Ratio BER of a device against a maximal allowable (Bit) Error Ratio BER limit with an early pass and/or early fail criterion, whereby the early pass and/or...
7512850 Checkpointing user design states in a configurable IC  
Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values....
7512846 Method and apparatus of defect areas management  
A method and the apparatus of defect areas management includes the steps as following: reading a defect area table in a random access memory; if the area is readable, then read the area. If the...
7512847 Method for estimating and reporting the life expectancy of flash-disk memory  
A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation...
7509547 System and method for testing of interconnects in a programmable logic device  
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the...
7509545 Method and system for testing memory modules  
A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two...
7506226 System and method for more efficiently using error correction codes to facilitate memory device testing  
A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate...
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