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7627843 Dynamically interleaving randomly generated test-cases for functional verification  
The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct...
7627798 Systems and methods for circuit testing using LBIST  
Systems and methods for performing logic built-in-self-tests (LBISTS) in digital circuits. In one embodiment, the operation of LBIST circuitry is suspended at the end of each test cycle so that the...
7610531 Modifying a test pattern to control power supply noise  
Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a...
7610527 Test output compaction with improved blocking of unknown values  
Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control...
7610526 On-chip circuitry for bus validation  
Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus,...
7600169 Systems and methods of test case generation with feedback  
Systems and methods for implementing test case generation with feedback are disclosed. An exemplary system for test case generation with feedback comprises a plurality of knobs identifying test...
7526703 Method of test pattern generation in IC design simulation system  
The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each...
7523367 Method and apparatus to verify non-deterministic results in an efficient random manner  
The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a...
7519889 System and method to reduce LBIST manufacturing test time of integrated circuits  
A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array...
7519886 Apparatus and method for integrated functional built-in self test for an ASIC  
We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based...
7490281 Segmented algorithmic pattern generator  
A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow...
7490275 Method and apparatus for evaluating and optimizing a signaling system  
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive...
7487419 Reduced-pin-count-testing architectures for applying test patterns  
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed...
7486725 Bit error rate tester and pseudo random bit sequences generator thereof  
A bit error rate tester and a pseudo random bit sequences (PRBS) generator thereof are provided. The bit error rate tester includes a transmitter PRBS generator, a master PRBS generator, a slave...
7484151 Method and apparatus for testing logic circuit designs  
Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is...
7478304 Apparatus for accelerating through-the-pins LBIST simulation  
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device  
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
7475317 Automatic test pattern generation  
A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is...
7461308 Method for testing semiconductor chips by means of bit masks  
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
7454680 Method, system and computer program product for improving efficiency in generating high-level coverage data for a circuit-testing scheme  
A method, system and computer program product for generating a coverage model to describe a testing scheme for a simulated system are described. In a preferred embodiment, a simulated system is...
7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7447966 Hardware verification scripting  
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification...
7447954 Method of testing a memory module and hub of the memory module  
A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module,...
7444558 Programmable measurement mode for a serial point to point link  
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link....
7441172 DVI link with parallel test data  
An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit....
7437261 Method and apparatus for testing integrated circuits  
A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of...
7424417 System and method for clock domain grouping using data path relationships  
A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains...
7421637 Generating test input for a circuit  
Generating test input includes initializing a current pseudo-random value at a test input generator coupled to a circuit component. Write data is received from the circuit component. The following...
7421629 Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure  
The invention relates to a semi-conductor component test procedure, and a semiconductor component test device ( 10 b ), which comprise: a device ( 43 ) for generating pseudo-random address...
7415648 Method and system for testing a network interface  
A method for testing a network interface is provided that includes generating a data pattern file based on a pseudocode file and testing the interface using the data pattern file. The pseudocode...
7412640 Self-synchronizing pseudorandom bit sequence checker  
Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in...
7404115 Self-synchronising bit error analyser and circuit  
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus...
7386776 System for testing digital components  
In order to test digital modules with functional elements, these are divided into test units ( 3 ) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of...
7366650 Software and hardware simulation  
A verification environment is provided that co-verifies a software component 8 and a hardware component 10 . Within the same environment using a common test controller 18 both hardware stimuli...
7363567 System and method for electronic device testing using random parameter looping  
Disclosed is a system and method for testing electronic devices which uses a random pattern for testing electronic devices. In one embodiment there is communicated to a device under test (DUT) a...
7360138 Verification of the design of an integrated circuit background  
A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and...
7343533 Hub for testing memory and methods thereof  
A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based...
7333518 Transmission method and transmission system as well as communications device  
A transmission method according to the present invention is capable of transmitting and receiving a data signal and information signal among a plurality of devices by full-duplex operation,...
7325182 Method and circuit arrangement for testing electrical modules  
The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test...
7315973 Method and apparatus for choosing tests for simulation and associated algorithms and hierarchical bipartite graph data structure  
An apparatus for and method of generating test cases for testing simulated logic circuit designs. The test cases are basically generated automatically in a random fashion, manually, or using some...
7313738 System and method for system-on-chip interconnect verification  
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear...
7299394 Method and apparatus for determining optimum initial value for test pattern generator  
The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this...
7299392 Semiconductor integrated circuit device and method of design of semiconductor integrated circuit device  
A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device...
7298779 Fast code acquisition method based on signed-rank statistic  
The present invention relates to the fast code acquisition methods based on signed-rank statistic. In more detail, it presents novel detectors required for PN (PN) code acquisition in DS/SS system....
7284177 Method and apparatus for functionally verifying a physical device under test  
Method, apparatus, and computer readable medium for functionally verifying a physical device under test (DUT) is described. In one example, verification test data is generated for the physical DUT...
7275195 Programmable built-in self-test circuit for serializer/deserializer circuits and method  
A built-in self-test circuit for use in testing a serializer/deserializer circuit includes a programmable transmit register that transmits data to the serializer/deserializer circuit having...
7272756 Exploitive test pattern apparatus and method  
Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or...
7269773 Test program debugger device, semiconductor test apparatus, test program debugging method and test method  
A test program debugging apparatus of the present invention includes a device under test simulator and a semiconductor testing apparatus simulator. Further, the semiconductor testing apparatus...
7263478 System and method for design verification  
An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility...
7246293 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Method and apparatus for functionally verifying a physical device under test  
Method, apparatus, and computer readable medium for functionally verifying a physical device under test (DUT) is described. In one example, verification test data is generated for the physical DUT...
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