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7620865 |
Scan string segmentation for digital test compression
One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip to achieve improved test vector compression, and one may combine this technique with methods to...
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7620861 |
Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
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7617468 |
Method for automatic maximization of coverage in constrained stimulus driven simulation
A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit....
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7613973 |
Method for providing bitwise constraints for test generation
A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a...
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7613964 |
Relay device and corresponding method
The invention consists of a relay device including: at least one mode change device for changing the relay device from a normal mode to a test mode; an interface for receiving test script from a...
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7612575 |
Electronic device test apparatus for successively testing electronic devices
An apparatus having a plurality of test units ( 520 ), a loading transport unit ( 510 ) transporting a plurality of electronic devices from a customer tray ( 4 C) to a test tray ( 4 T) before being...
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7610539 |
Method and apparatus for testing logic circuit designs
Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is...
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7610531 |
Modifying a test pattern to control power supply noise
Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a...
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7610530 |
Test data generator, test system and method thereof
A test data generator, test system and method thereof are provided. In the example method, parallel test data may be received at a first data rate. The received parallel test data may be converted...
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7610527 |
Test output compaction with improved blocking of unknown values
Implementations of the present principles are directed to test output compaction arrangements and a methods of generating control patterns for unknown blocking. The specified bits in the control...
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7610526 |
On-chip circuitry for bus validation
Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus,...
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7607056 |
Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation...
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7607055 |
Semiconductor memory device and method of testing the same
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
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7603604 |
Test apparatus and electronic device
A test apparatus that tests a device under test is provided. The test apparatus includes: a pattern memory that stores in a compression format a test instruction sequence to define a test sequence...
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7603603 |
Configurable memory architecture with built-in testing mechanism
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced...
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7603600 |
Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereon a timing failure diagnosing program for an integrated circuit, and computer readable recording medium recorded thereon a timing failure remedying program for an integrated circuit
A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core...
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7603595 |
Memory test circuit and method
A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and...
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7600169 |
Systems and methods of test case generation with feedback
Systems and methods for implementing test case generation with feedback are disclosed. An exemplary system for test case generation with feedback comprises a plurality of knobs identifying test...
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7596731 |
Test time reduction algorithm
Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of...
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7596729 |
Memory device testing system and method using compressed fail data
A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device....
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7590903 |
Re-configurable architecture for automated test equipment
An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit...
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7587651 |
Method and related apparatus for calibrating signal driving parameters between chips
A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test...
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7587646 |
Test pattern generation in residue networks
Generating a near-minimal test pattern set for overlapping residue circuit trees in a residue network includes resolving a residue function of residue circuits through the network and making note...
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7587645 |
Input circuit of semiconductor memory device and test system having the same
An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by...
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7584395 |
Systems, methods and apparatus for synthesizing state events for a test data stream
In one embodiment, a method of has the steps of A) accessing a stream of test data comprising 1) a number of state events and 2) a number of data events interspersed with the ones of the state...
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7584394 |
System and method for pseudo-random test pattern memory allocation for processor design verification and validation
A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described...
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7581207 |
Method of configuring managed entities in a communications network using configuration templates
The advantages are derived from a cost-reduced managed entity configuration of various communications network equipment having diverse makes, models, and software releases. Expertise of highly...
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7576554 |
Semiconductor devices and methods of testing the same
A semiconductor device may include a plurality of output electrodes configured to provide electrical coupling for a respective plurality of output signals outside the semiconductor device. A signal...
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7574644 |
Functional pattern logic diagnostic method
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
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7574633 |
Test apparatus, adjustment method and recording medium
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
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7571363 |
Parametric measurement of high-speed I/O systems
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
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7568134 |
Method of exhaustively testing an embedded ROM using generated ATPG test patterns
A model of the memory device is provided, including a memory array model having a plurality of memory array model locations, and a plurality of decoder models, each associated with a memory array...
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7565591 |
Testing of circuits with multiple clock domains
Consistent with an example embodiment, the amount of time required for testing circuits that contain a plurality of different clock domains is reduced. According to the embodiment, during selection...
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7565578 |
Optical disc apparatus, and method for self-diagnosis control of optical disc apparatus
An optical disc apparatus capable of performing self-diagnosis receives from a host computer a command to enable a self-diagnostic mode. Information indicating that the self-diagnosis mode is...
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7559001 |
Method and apparatus for executing commands and generation of automation scripts and test cases
A command execution terminal includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses and maintaining a...
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7559000 |
Integrated circuit device, diagnosis method and diagnosis circuit for the same
Hardware diagnosis of a disk array apparatus is conducted before shipment by using a self-diagnosis circuit, using the same criteria that apply to actual in-use equipment. A logical circuit and a...
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7558994 |
Methods and apparatus for data compression
A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including...
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7558991 |
Device and method for measuring jitter
A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency f s at its output. A phase modulator generates a test clock...
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RE40823 |
Method for bit error rate measurements in a cell-based telecommunication system
A method for bit error rate measurements in a cell-based telecommunication system is presented, comprising the following steps of generating a first bit pattern at a first location of said...
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7555685 |
Method and apparatus for monitoring bit-error rate
A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be...
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7549101 |
Clock transferring apparatus, and testing apparatus
There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of...
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7546506 |
DRAM stacked package, DIMM, and semiconductor manufacturing method
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM...
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7546499 |
Communication signal testing with a programmable logic device
Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test...
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7536621 |
Quantized data-dependent jitter injection using discrete samples
Methods, system, and computer programs for compensating for introducing data dependent jitter into a test signal using a testing instrument are disclosed. The method includes generating a test...
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7536620 |
Method of and apparatus for validation support, computer product for validation support
An information input unit inputs functional configuration information representing a function of a device to be validated. A condition input unit inputs conditions concerning input/output sequence...
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7533318 |
Test pattern generator and test pattern generation method for onboard memory devices
A test pattern generator generating a test pattern for performance testing of an onboard memory is provided for a device having a memory macro, a serial input interface, and a latch circuit...
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7533317 |
Serializer/deserializer circuit for jitter sensitivity characterization
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
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7529989 |
Testing apparatus and testing method
A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under...
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7529294 |
Testing of multiple asynchronous logic domains
A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator...
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7526703 |
Method of test pattern generation in IC design simulation system
The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each...
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