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7624317 |
Parallel bit test circuit and method for semiconductor memory device
A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory...
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7620884 |
Memory checking device and method for checking a memory
A memory checking device for cells arranged in memory rows and columns, wherein, in a state of integrity, the memory has parity values for two memory rows or two columns that differ from each other...
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7620869 |
Semiconductor integrated circuit and BIST circuit design method
A semiconductor integrated circuit comprising a plurality of memory circuits; a BSIT circuit 140 operable to output test vectors; and one or more register circuit(s) 150 each allocated on a...
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7620868 |
Method for detecting a malfunction in a state machine
A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine...
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7620861 |
Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication...
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7617426 |
Verification method and apparatus
A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc;...
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7617425 |
Method for at-speed testing of memory interface using scan
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
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7613974 |
Fault detection method and apparatus
This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a...
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7612698 |
Test apparatus, manufacturing method, and test method
There is provided a test apparatus for testing a device under test, the test apparatus including: a test signal supplying section that supplies a digital input signal for testing purposes, to the...
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7607056 |
Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation...
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7603598 |
Semiconductor device for testing semiconductor process and method thereof
A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing...
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7602744 |
Detection of a simultaneous occurrence of an event at a plurality of devices
The invention relates to a detection of a simultaneous occurrence of an event of a predetermined kind at a plurality of electronic devices. At least two devices detect the event and record at their...
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7590911 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the...
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7584391 |
Smart verify for multi-state memories
A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify...
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7577738 |
Method and apparatus using voice and data attributes for probe registration and network monitoring systems
The present invention is directed to network monitoring systems. Test probes available for use in connection with network monitoring are registered. As part of the registration of test probes,...
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7574644 |
Functional pattern logic diagnostic method
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
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7568143 |
System and method of utilizing a network to correct flawed media data
A system and method of utilizing a network to correct flawed media data. The media device includes a processor, a memory, a network adapter, a removable media interface, an error-correction module,...
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7559003 |
Semiconductor memory test apparatus
A semiconductor memory test apparatus has a log data generating unit for generating log data indicating a test result of a device under test based on output data from the device under test...
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7558993 |
Test apparatus for semiconductor memory device
A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output...
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7552355 |
System for providing an alternative communication path in a SAS cluster
The present invention is directed to a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node...
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7546506 |
DRAM stacked package, DIMM, and semiconductor manufacturing method
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM...
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7539903 |
Method for monitoring the execution of a program by comparing a request with a response and introducing a falsification in a response
The invention relates to a method for monitoring the execution of a program in a microcomputer of an electronic device, especially a sensor circuit for motor vehicles. According to the inventive...
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7536619 |
RAM testing apparatus and method
Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be...
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7533314 |
Unit test extender
A unit test extending system and method use a unit test extender engine and a test pattern to extend a unit test written to validate code under test. The unit test has a first function configured...
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7519889 |
System and method to reduce LBIST manufacturing test time of integrated circuits
A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array...
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7519886 |
Apparatus and method for integrated functional built-in self test for an ASIC
We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based...
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7516383 |
Method and apparatus for analyzing delay in circuit, and computer product
An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated...
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7516382 |
On-chip data transmission control apparatus and method
The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is...
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7509552 |
Multi-thread parallel segment scan simulation of chip element performance
A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a...
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7509547 |
System and method for testing of interconnects in a programmable logic device
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the...
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7502992 |
Method and apparatus for detecting presence of errors in data transmitted between components in a data storage system using an I2C protocol
A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a...
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7500162 |
Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing
An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input...
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7496809 |
Integrated scannable interface for testing memory
An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first...
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7493543 |
Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing
Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are...
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7484156 |
Apparatus and method for testing PS/2 interface
An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock...
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7478304 |
Apparatus for accelerating through-the-pins LBIST simulation
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
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7478300 |
Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
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7478004 |
Method for testing a connection between an audio receiving device and a motherboard
A method for testing a connection between an audio receiving device and a motherboard is disclosed. The method includes the steps of: preparing a data storage medium containing an original audio...
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7475315 |
Configurable built in self test circuitry for testing memory arrays
Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The...
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7475311 |
Systems and methods for diagnosing rate dependent errors using LBIST
Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target...
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7475306 |
Scan test method, integrated circuit, and scan test circuit
A scan test method of an integrated circuit including a combinational circuit and flip-flops forming a scan chain is disclosed. The method first sets an initial test value to the flip-flops forming...
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7467343 |
Apparatus and method for performing a multi-value polling operation in a JTAG data stream
In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine...
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7467342 |
Method and apparatus for embedded built-in self-test (BIST) of electronic circuits and systems
An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The...
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7467339 |
Semiconductor integrated circuit and a method of testing the same
A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set...
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7461308 |
Method for testing semiconductor chips by means of bit masks
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
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7459926 |
Scan distributor loading scan paths simultaneous with loading test data
An integrated circuit ( 70 ) having parallel scan paths ( 824 - 842, 924 - 942 ) includes a pair or pairs of scan distributor ( 800,900 ) and scan collector ( 844,944 ) circuits. The scan paths...
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7454676 |
Method for testing semiconductor chips using register sets
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
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7449909 |
System and method for testing one or more dies on a semiconductor wafer
A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write...
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7447966 |
Hardware verification scripting
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification...
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7447955 |
Test apparatus and test method
There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data...
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