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9043665 Functional fabric based test wrapper for circuit testing of IP blocks  
A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller...
9041431 Partial reconfiguration and in-system debugging  
Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several...
9026872 Flexible sized die for use in multi-die integrated circuit  
An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base...
9013204 Test system and test method for PCBA  
A test system is provided. A printed circuit board (PCB) includes a plurality of traces and at least one test point. A central processing unit (CPU) socket including a plurality of first pins and...
9015542 Packetizing JTAG across industry standard interfaces  
Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test...
9003253 Method for testing data packet signal transceiver using coordinated transmitted data packet signal power  
A method for testing a data packet signal transceiver device under test (DUT) that minimizes time lost due to waiting for respective power levels of data packets transmitted by the DUT to settle...
8990650 TCA with scan paths, decompressor, compressor, and output shift register  
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access...
8990649 Access port selector for access port and compliant access port  
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports...
8990651 Integrated circuit (IC) with primary and secondary networks and device containing such an IC  
Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The...
8977921 System and method for providing a test result from an integrated to an analyzer  
A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit....
8972811 Panel driving circuit that generates panel test pattern and panel test method thereof  
A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern...
8943457 Simulating scan tests with reduced resources  
An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data...
8930782 Root cause distribution determination based on layout aware scan diagnosis results  
Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a...
8918685 Test circuit, memory system, and test method of memory system  
This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention...
8914688 System and method of reducing test time via address aware BIST circuitry  
In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control...
8910003 Controller circuitry with state machines, address store/compare, and shift register  
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and...
8904250 Autorecovery after manufacturing/system integration  
Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting...
8880969 Switching converter with pulse skipping mode and control method thereof  
The present invention provides a switching converter with pulse skipping mode. The switching converter comprises a switching circuit having at least one switch, a controller and a feedback...
8872531 Semiconductor device and test apparatus including the same  
A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal...
8862949 Systems and methods for storing information  
Embodiments relate to reliably storing information in a sensor or other device. In an embodiment, information storage circuitry comprises independent, redundant memory portions and error detection...
8839056 Equipment testing method and apparatus  
Systems, methods, and devices related to testing receive equipment. A test signal generator is coupled to both a receiver and an antenna. The receiver is also coupled to the antenna and a test...
8832499 Methods and structure for trapping requests directed to hardware registers of an electronic circuit  
Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that...
8829940 Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device  
The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test...
8825433 Automatic generation of valid at-speed structural test (ASST) test groups  
A method and system is provided for automatically generating valid at speed structural test (ASST) test groups. The method includes loading a netlist for an integrated circuit into a processor....
8826086 Memory card test interface  
A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have...
8826091 Die with DIO path, clock input, TLM, and TAP domains  
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2)...
8819510 Selectable JTAG or trace access with data store and output  
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and...
8819511 Methods and systems for an automated test configuration to identify logic device defects  
Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic...
8813019 Optimized design verification of an electronic circuit  
A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also...
8812936 Using slow response memory device on a fast response interface  
A method includes receiving a request to read data at a data storage device from an external device. In response to determining that the data is in a first memory of the data storage device, a...
8803716 Memoryless sliding window histogram based BIST  
A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram...
8793547 3D built-in self-test scheme for 3D assembly defect detection  
Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described...
8782480 On-chip functional debugger and a method of providing on-chip functional debugging  
An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the...
8775881 Embedded processor  
Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other...
8762801 Method and system for detecting and repairing defective memory cells without reporting a defective memory cell  
A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective...
8751887 Enable gating clock, shift, capture, and update to first gating  
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual...
8751886 Enable gating select signal to P1500 IR and DR gating  
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual...
8745457 Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signals  
Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit...
8742779 Semiconductor device and abnormality prediction method thereof  
A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of...
8738979 Methods and structure for correlation of test signals routed using different signaling pathways  
Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable...
8732540 Semiconductor device having input/output wrappers, and a method of controlling the wrappers  
A semiconductor device include a first wrapper including a first scan flip-flop, first control flip-flops and a first pad, the first scan flip-flop receiving a first value and second values and...
8723539 Test card for motherboards  
A test card includes a power interface, a controller, a test interface, and a test point. The test interface includes a power pin, a start pin, and a data signal pin. The power interface is...
8726112 Scan test application through high-speed serial input/outputs  
Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol...
8713389 Tap and linking module TDO register, gating for TCK and TMS  
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and...
8713391 System and method for testing an integrated circuit embedded in a system on a chip  
A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is...
8707118 Data, mode and ready bit packets on bidirectional control/data leads  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
8707115 Micro controller, driving method thereof and display device using the same  
A micro controller includes an input and output unit having a reset terminal, a plurality of input terminals, and a test enable terminal, a test mode setting unit which allocates a first input...
8686753 Partial reconfiguration and in-system debugging  
Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several...
8683280 Test generator for low power built-in self-test  
Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle...
8677200 Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testing  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises transition control circuitry...