|
Match
|
Document |
Document Title |
|
|
7617425 |
Method for at-speed testing of memory interface using scan
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
|
|
|
7612574 |
Systems and methods for defect testing of externally accessible integrated circuit interconnects
Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for...
|
|
|
7610537 |
Method and apparatus for testing multi-core microprocessors
A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces...
|
|
|
7607060 |
System and method for performing high speed memory diagnostics via built-in-self-test
A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a...
|
|
|
7607055 |
Semiconductor memory device and method of testing the same
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the...
|
|
|
7603602 |
Built-in self test circuit for analog-to-digital converter and phase lock loop and the testing methods thereof
A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge...
|
|
|
7603601 |
Enabling special modes within a digital device
A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a...
|
|
|
7603600 |
Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereon a timing failure diagnosing program for an integrated circuit, and computer readable recording medium recorded thereon a timing failure remedying program for an integrated circuit
A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core...
|
|
|
7603598 |
Semiconductor device for testing semiconductor process and method thereof
A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing...
|
|
|
7603596 |
Memory device capable of detecting its failure
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
|
|
|
7596737 |
System and method for testing state retention circuits
This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a...
|
|
|
7596731 |
Test time reduction algorithm
Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of...
|
|
|
7596728 |
Built-in self repair circuit for a multi-port memory and method thereof
A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to...
|
|
|
7594150 |
Fault-tolerant architecture of flip-flops for transient pulses and signal delays
A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and...
|
|
|
7590912 |
Using a chip as a simulation engine
The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and...
|
|
|
7590911 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the...
|
|
|
7590905 |
Method and apparatus for pipelined scan compression
A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation...
|
|
|
7590901 |
Apparatus, system, and method for dynamic recovery and restoration from design defects in an integrated circuit
An apparatus, system, and method are disclosed for the recovery from a design defect in an integrated circuit. The apparatus includes an error check module, a control settings module, a retry...
|
|
|
7590504 |
Graphical user interface for creation of IBIST tests
A graphical user interface (GUI) that configures a test for a circuit. More particularly, the circuit includes a built-in-self-test (BIST) compatible device and has a test configuration. The device...
|
|
|
7587648 |
Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test...
|
|
|
7587202 |
Method for conducting digital interface and baseband circuitry tests using digital loopback
In a mobile device having a primary baseband circuit and a secondary baseband circuit and an interface between the primary baseband circuit and a secondary baseband circuit, a method for testing...
|
|
|
7581152 |
Fault free store data path for software implementation of redundant multithreading environments
A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software...
|
|
|
7581151 |
Method and apparatus for affecting a portion of an integrated circuit
In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or...
|
|
|
7574643 |
Test apparatus and method for testing a circuit unit
In a method for testing an electric circuit comprising circuit subunits, the electric circuit is connected to a test system via a tester channel with a connection unit. The tester channel is...
|
|
|
7574642 |
Multiple uses for BIST test latches
A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in...
|
|
|
7571367 |
Built-in self diagnosis device for a random access memory and method of diagnosing a random access
A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of...
|
|
|
7570076 |
Segmented programmable capacitor array for improved density and reduced leakage
A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal ( 100 ), a plurality of circuit elements ( 322,...
|
|
|
7568141 |
Method and apparatus for testing embedded cores
The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the...
|
|
|
7565589 |
Semiconductor integrated circuit having a BIST circuit
A semiconductor integrated circuit, includes a first external terminal which inputs a test signal, a second external terminal which external inputs a clock signal, a self-test circuit which...
|
|
|
7565585 |
Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system
An integrated redundancy architecture for an embedded memory system whereby a third memory element is added to the redundancy architecture such that all row and column fails may be stored in...
|
|
|
7565578 |
Optical disc apparatus, and method for self-diagnosis control of optical disc apparatus
An optical disc apparatus capable of performing self-diagnosis receives from a host computer a command to enable a self-diagnostic mode. Information indicating that the self-diagnosis mode is...
|
|
|
7562276 |
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit (IC) comprises an embedded processor. An embedded in-circuit emulator (ICE) emulates at least one function of the embedded processor, performs at least one of testing and...
|
|
|
7562274 |
User data driven test control software application the requires no software maintenance
Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using...
|
|
|
7549098 |
Redundancy programming for a memory device
A method for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, test patterns are...
|
|
|
7548828 |
Automatic test equipment platform architecture using parallel user computers
The present invention provides a system of testing semiconductor devices. The system comprises a central host computer, an array of user computers (the array), and a HU (Host-User) network as the...
|
|
|
7546505 |
Built in self test transport controller architecture
A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive...
|
|
|
7546504 |
System and method for advanced logic built-in self test with selection of scan channels
A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or...
|
|
|
7546501 |
Selecting test circuitry from header signals on power lead
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure,...
|
|
|
7543209 |
Characterizing jitter sensitivity of a serializer/deserializer circuit
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
|
|
|
7543198 |
Test data reporting and analyzing using data array and related data analysis
Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array. One method includes obtaining the test data, and reporting the test data in a data array,...
|
|
|
7541815 |
Electronic device, testing apparatus, and testing method
A testing apparatus tests the performance of an electronic device having an operation circuit for providing a useful output signal. A demodulator configured to provide a phase or frequency...
|
|
|
7539910 |
Memory module test system for memory module including hub
A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester...
|
|
|
7536614 |
Built-in-redundancy analysis using RAM
A method for testing memory in an integrated circuit device is disclosed. The method includes executing a test routine in a portion of the memory at a speed sufficient to fully test the memory...
|
|
|
7533317 |
Serializer/deserializer circuit for jitter sensitivity characterization
Disclosed herein is an improved serializer/deserializer (SERDES) circuit ( 102 ) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization...
|
|
|
7533316 |
Method and apparatus for disabling and swapping cores in a multi-core microprocessor
In some embodiments, a method and apparatus for disabling and swapping cores in a multi-core microprocessor are presented. In this regard, a test agent is introduced to disable a core, to configure...
|
|
|
7533315 |
Integrated circuit with scan-based debugging and debugging method thereof
An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the...
|
|
|
7529998 |
Runtime reconfiguration of reconfigurable circuits
A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.
|
|
|
7529997 |
Method for self-correcting cache using line delete, data logging, and fuse repair correction
An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are...
|
|
|
7529989 |
Testing apparatus and testing method
A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under...
|
|
|
7526700 |
Semiconductor integrated circuit device
Provided are external input/output signal terminals, an interface circuit including a plurality of unit input/output circuits accompanying the respective signal terminals, a memory macro, a BIST...
|