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7339389 |
Semiconductor device incorporating characteristic evaluating circuit operated by high frequency clock signal
In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than...
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7337380 |
Eye width characterization mechanism
An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from...
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7337378 |
Semiconductor integrated circuit and burn-in test method thereof
To provide a semiconductor integrated circuit that includes a flash EEPROM on which an efficient burn-in test can be carried out and a burn-in test method thereof. By changing the level of a...
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7330993 |
Slew rate control mechanism
According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the...
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7328388 |
Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement ( 60 ). The built-in self-test arrangement includes a read only memory (ROM), ( 140 ) that stores test algorithm instructions. A...
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7328382 |
Memory BISR controller architecture
The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The...
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7324392 |
ROM-based memory testing
This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each...
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7322000 |
Methods and apparatus for extending semiconductor chip testing with boundary scan registers
Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an...
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7319624 |
Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof
A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test...
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7318182 |
Memory array manufacturing defect detection system and method
The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received...
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7315970 |
Semiconductor device to improve data retention characteristics of DRAM
A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and...
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7313738 |
System and method for system-on-chip interconnect verification
A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear...
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7313742 |
Logic circuitry having self-test function
A logic circuit having a self-test function includes a plurality of F/Fs having at least first-, second- and last-stage scanning F/Fs, each having a clock input, a scanning input and a scanning...
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7313740 |
Internally generating patterns for testing in an integrated circuit device
In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address...
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7308634 |
Systems and methods for LBIST testing using multiple functional subphases
Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional...
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7308621 |
Testing of ECC memories
A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A...
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7308633 |
Master controller architecture
A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem...
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7305597 |
System and method for efficiently testing a large random access memory space
A system for, and method of, allowing conventional memory test circuitry to test parallel memory arrays and an integrated circuit incorporating the system or the method. In one embodiment, the...
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7305596 |
Nonvolatile memory and nonvolatile memory apparatus
To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the...
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7302622 |
Integrated memory having a test circuit for functional testing of the memory
An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of...
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7302625 |
Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration
A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The...
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7296202 |
Semiconductor module with a configuration for the self-test of a plurality of interface circuits and test method
A semiconductor module with a plurality of interface circuits has a configuration for the self-test of interface circuits, with two equally sized groups of interface circuits such that each...
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7293212 |
Memory self-test via a ring bus in a data processing apparatus
A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being...
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7293199 |
Method and apparatus for testing memories with different read/write protocols using the same programmable memory bist controller
A method of testing a plurality of embedded memories within an integrated circuit. Each of the embedded memories include particular read and write protocols. The method includes providing a memory...
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7290186 |
Method and apparatus for a command based bist for testing memories
Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories....
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7284166 |
Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of...
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7281184 |
Test system and method for testing a circuit
A test-device for testing an electric circuit comprises a data stream generator for generating a first data stream to be fed to an electric circuit which generates a second data stream in response...
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7278077 |
IBIST test for synchronous lines at multiple frequencies
A system for testing a synchronous link utilizing a single test pattern sequence. Components coupled via a link are each configured to generate and check test patterns according to a single...
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7274203 |
Design-for-test circuit for low pin count devices
A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator...
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7274199 |
Method and arrangement of testing device in mobile station
The invention relates to a method and an arrangement of testing a device, such as a peripheral device, in a mobile station. The arrangement comprises a signal generator for generating a test signal...
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7274200 |
Semiconductor circuit, method of monitoring semiconductor-circuit performance, method of testing semiconductor circuit, equipment for testing semiconductor circuit, and program for testing semiconductor circuit
A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay...
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7275195 |
Programmable built-in self-test circuit for serializer/deserializer circuits and method
A built-in self-test circuit for use in testing a serializer/deserializer circuit includes a programmable transmit register that transmits data to the serializer/deserializer circuit having...
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7272756 |
Exploitive test pattern apparatus and method
Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or...
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7272763 |
Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices
A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any...
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7269772 |
Method and apparatus for built-in self-test (BIST) of integrated circuit device
An integrated circuit device ( 200 ) can include a main portion ( 204 ) and a built-in self-test (BIST) portion ( 204 ) having outputs coupled to physical input structures (e.g., bond pads) ( 206 )...
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7269529 |
Data processing apparatus, program, and method for testing a secured circuit and maintaining confidentiality of the circuit
A data processing apparatus that tests whether a secure circuit is normal or not while maintaining confidentiality of the secured circuit is provided: wherein the secured circuit conducts a...
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7266743 |
Combinatorial at-speed scan testing
A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first...
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7266737 |
Method for enabling scan of defective ram prior to repair
A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable...
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7266745 |
Programmable scan shift speed control for LBIST
Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a...
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7263286 |
Fast testing system for optical transceiver and testing method thereof
The present invention provides a fast testing system and method for optical transceiver, which integrates multiple testing machines in the testing environment for the optical transceiver, so that...
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7260759 |
Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors
A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics...
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7260757 |
System and method for testing electronic devices on a microchip
A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple...
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7260755 |
Skewed inverter delay line for use in measuring critical paths in an integrated circuit
An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay...
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7257745 |
Array self repair using built-in self test techniques
A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad...
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7257752 |
Circuit and method for performing built-in self test and computer readable recording medium for storing program thereof
A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a...
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7256600 |
Method and system for testing semiconductor devices
A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a...
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7257751 |
Apparatus and method for random pattern built in self-test
An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a...
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7254753 |
Circuit and method for configuring CAM array margin test and operation
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or...
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7254762 |
Semiconductor integrated circuit
A semiconductor integrated circuit includes: a logic circuit to be tested; a memory connected the logic circuit to be tested; a BIST circuit for testing the memory; and a bypass circuit connected...
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7254759 |
Methods and systems for semiconductor defect detection
A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for...
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