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7404125 Compilable memory structure and test methodology for both ASIC and foundry test environments  
A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one...
7401277 Semiconductor integrated circuit and scan test method therefor  
A method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested. The method includes isolating each of the at least two blocks to be tested...
7401271 Testing system and method of using same  
A testing system (and method of using same) for testing a system-under-test (SUT) are provided. One embodiment of the testing system includes first, second, and third logic sections. The third...
7401281 Remote BIST high speed test and redundancy calculation  
Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed...
7398443 Automatic fault-testing of logic blocks using internal at-speed logic-BIST  
System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an...
7397263 Sensor differentiated fault isolation  
Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.)...
7395475 Circuit and method for fuse disposing in a semiconductor memory device  
A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test...
7395474 Lab-on-chip system and method and apparatus for manufacturing and operating same  
A lab-on-chip system comprises an antenna and a communications subsystem to wirelessly transmit information from the lab-on-chip system. The communications subsystem may also receive information,...
7395466 Method and apparatus to adjust voltage for storage location reliability  
According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at...
7389458 Method and apparatus for the memory self-test of embedded memories in semiconductor chips  
Method for the memory self-test of embedded memories ( 2, 3, 4 ) in semiconductor chips ( 1 ), a memory address range ( 8 ) being assigned to a memory ( 2 ) to be tested and addresses from the same...
7389455 Register file initialization to prevent unknown outputs during test  
A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized...
7389460 Runtime-competitive fault handling for reconfigurable logic devices  
Methods, systems, apparatus and devices to provide autonomous self-repair for programmable logic. Using Competitive Runtime Reconfiguration, an initial population of functionally identical, yet...
7389454 Error detection in user input device using general purpose input-output  
A method and apparatus are disclosed for using a general purpose input-output (GPIO) interface to test a user input device such as a wireless keyboard or mouse. Operation of key-scan logic can be...
7389459 Provision of debug via a separate ring bus in a data processing apparatus  
A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the...
7386776 System for testing digital components  
In order to test digital modules with functional elements, these are divided into test units ( 3 ) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of...
7382148 System and method for testing an LED and a connector thereof  
A system for testing a light emitting diode (LED) ( 20 ) and connectors thereof. The system includes: a chip ( 10 ) having general purpose input output (GPIO) function and a plurality of pins ( 101...
7383481 Method and apparatus for testing a functional circuit at speed  
An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional...
7380180 Method, system, and apparatus for tracking defective cache lines  
To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a...
7380190 RFID tag with bist circuits  
Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for...
7380152 Daisy chained multi-device system and operating method  
A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the...
7380191 ABIST data compression and serialization for memory built-in self test of SRAM with redundancy  
A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for...
7376875 Method of improving logical built-in self test (LBIST) AC fault isolations  
A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to...
7376889 Memory device capable of detecting its failure  
A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for...
7375540 Process monitor for monitoring and compensating circuit performance  
A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated...
7373569 Pulsed flop with scan circuitry  
In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected...
7373573 Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing  
An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy...
7373574 Semiconductor testing apparatus and method of testing semiconductor  
A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test...
7370257 Test vehicle data analysis  
A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one...
7368931 On-chip self test circuit and self test method for signal distortion  
There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on...
7370249 Method and apparatus for testing a memory array  
A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is...
7370254 Compressing test responses using a compactor  
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can...
7366953 Self test method and apparatus for identifying partially defective memory  
A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a...
7363563 Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers  
Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a...
7359820 In-cycle system test adaptation  
Disclosed are a method, information processing system and computer readable medium for performing a system test on a program. The method comprises creating a test plan associated with a system...
7360135 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance  
An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit...
7360134 Centralized BIST engine for testing on-chip memory structures  
One embodiment of the present invention provides a system that uses a single built-in-self-test (BIST) engine to test multiple on-chip memory structures. During chip-test or power-on-self-test in...
7356743 RRAM controller built in self test memory  
An RRAM design having linear BIST memory and rectangular BIST memory, the improvement comprising at least one of the linear BIST memory and the rectangular BIST memory formed only of flipflops and...
7356741 Modular test controller with BIST circuit for testing embedded DRAM circuits  
A modular test controller with a built-in self-test (BIST) circuit for testing an embedded DRAM (eDRAM) circuit is provided. The test controller includes a built-in self-test (BIST) core for...
7356746 Embedded testing circuit for testing a dual port memory  
A circuit tests a memory having a cell array accessible through first and second ports, the circuit comprising an address generation circuit for generating an internal address consisting of a row...
7353442 On-chip and at-speed tester for testing and characterization of different types of memories  
An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically...
7353474 System and method for accessing signals of a user design in a programmable logic device  
Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler,...
7353162 Scalable reconfigurable prototyping system and method  
A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The...
7350124 Method and apparatus for accelerating through-the pins LBIST simulation  
The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set...
7346824 Match circuit for performing pattern recognition in a performance counter  
A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data...
7346822 Integrated circuit  
An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to...
7346823 Automatic built-in self-test of logic with seeding from on-chip memory  
Built-in self-test (BIST) devices and methods are disclosed. A BIST section ( 100 ) according to one embodiment can include a built-in seed value memory ( 150 ) that stores multiple seed values. In...
7343535 Embedded testing capability for integrated serializer/deserializers  
Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested...
7343622 Multi-level secure multi-processor computer architecture  
A multi-level secure multi-processor computer architecture. The inventive architecture provides an inexpensive security solution for integrated avionics and includes a plurality of nodes. The nodes...
7340662 GBit/s transceiver with built-in self test features  
GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a...
7339388 Intra-clip power and test signal generation for use with test structures on wafers  
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of...
Matches 151 - 200 out of 1014 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >