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7475312 Integrated circuit (IC) with on-board characterization unit  
Consistent with example embodiments, there is a system and method for providing a built-in characterization of a semiconductor device. The device is provided with a built-in, integral,...
7475314 Mechanism for read-only memory built-in self-test  
In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by...
7472325 Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions  
Disclosed is a method for segmenting functionality of a hybrid built-in self test (BIST) architecture for embedded memory arrays into remote lower-speed executable instructions and local...
7472324 Logic built-in self-test channel skipping during functional scan operations  
A method and system for built-in self-testing architecture, including: a logic built-in self-test (LBIST) controller in operable communication with a pseudo-random pattern generator; a multiple...
7466157 Contactless interfacing of test signals with a device under test  
An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface...
7467342 Method and apparatus for embedded built-in self-test (BIST) of electronic circuits and systems  
An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The...
7463140 Systems and methods for testing wireless devices  
Systems and methods are disclosed for parallel testing one or more wireless devices using a single wireless command, each device including a processor and memory coupled to the processor. The...
7461312 Digital signature generation for hardware functional test  
A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period...
7461308 Method for testing semiconductor chips by means of bit masks  
A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test...
7458005 System and method for providing adjustable read margins in a semiconductor memory  
A system and method for effectuating a self-timed clock (STC) loop for memory access operations. In one embodiment, the method includes configuring a particular access margin value setting based on...
7458000 Automatic shutdown or throttling of a bist state machine using thermal feedback  
A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are...
7454676 Method for testing semiconductor chips using register sets  
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m...
7454727 Method and Apparatus for Solving Sequential Constraints  
Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior....
7447964 Difference signal path test and characterization circuit  
A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test...
7447956 Method and apparatus for testing data steering logic for data storage having independently addressable subunits  
Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to...
7444573 VLCT programmation/read protocol  
An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit...
7444558 Programmable measurement mode for a serial point to point link  
A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link....
7444564 Automatic bit fail mapping for embedded memories with clock multipliers  
A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE)...
7444572 Built-in self test for a thermal processing system  
A method of creating and/or modifying a built-in self test (BIST) table for monitoring a thermal processing system in real-time that includes positioning a plurality of wafers in a processing...
7444565 Re-programmable COMSEC module  
A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an...
7441167 Memory module with parallel testing  
Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a...
7441165 Read-only memory and operational control method thereof  
A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a...
7441169 Semiconductor integrated circuit with test circuit  
A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for...
7437643 Automated BIST execution scheme for a link  
Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training...
7437626 Efficient method of test and soft repair of SRAM with redundancy  
Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic...
7437644 Automatic self-testing of an internal device in a closed system  
A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system...
7434120 Test mode control circuit  
Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS...
7434131 Flexible memory built-in-self-test (MBIST) method and apparatus  
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more...
7428680 Programmable memory built-in-self-test (MBIST) method and apparatus  
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more...
7428682 Semiconductor memory device  
In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for...
7428683 Automatic analog test and compensation with built-in pattern generator and analyzer  
A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme...
7428679 Method for automated at-speed testing of high serial pin count multiple gigabit per second devices  
A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a...
7428674 Monitoring the state vector of a test access port  
Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The...
7428677 Boundary scan apparatus and interconnect test method  
An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design,...
7426668 Performing memory built-in-self-test (MBIST)  
Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more...
7424657 Method and device for testing an integrated circuit, integrated circuit to be tested, and wafer with a large number of integrated circuits to be tested  
A method and a device for testing an integrated circuit are defined by the fact that the testing of the integrated circuit is begun by a self-test device contained in the integrated circuit before...
7421635 System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC  
A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having...
7421384 Semiconductor integrated circuit device and microcomputer development supporting device  
During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in...
7421636 Semiconductor memory device having a test control circuit  
A semiconductor memory device having a test control circuit includes a cell array, a BIST (built-in self test) circuit adapted and configured to perform a BIST operation on the cell array, a BISR...
7421633 Controller receiving combined TMS/TDI and suppyling separate TMS and TDI  
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than...
7421629 Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure  
The invention relates to a semi-conductor component test procedure, and a semiconductor component test device ( 10 b ), which comprise: a device ( 43 ) for generating pseudo-random address...
7417449 Wafer stage storage structure speed testing  
A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory...
7418642 Built-in-self-test using embedded memory and processor in an application specific integrated circuit  
A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can...
7415646 Page—EXE erase algorithm for flash memory  
Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase...
7415643 Coverage circuit for performance counter  
A coverage circuit for use with a general purpose performance counter (“GPPC”) connected to a bus for capturing test coverage information encoded as N one-hot signals indicative of coverage in...
7412638 Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit  
A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes...
7409614 Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit  
A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the...
7406644 Monitoring a thermal processing system  
A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table to detect, diagnose and/or predict fault conditions and/or degraded performance. The method...
7406640 Method and apparatus for testing a ring of non-scan latches with logic built-in self-test  
A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An...
7406643 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium  
A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method...
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