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6255838 Apparatus and method for disabling and re-enabling access to IC test functions  
A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be...
6255835 Circuit for testing option of a semiconductor memory device  
There is disclosed an option function test apparatus of a semiconductor device including a function selecting means. The function selection means includes a fuse signal detecting section for...
6246618 Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof  
A semiconductor integrated circuit comprises many RAMs, a supplementary RAM, and test/repair control logic which detects a defective RAM out of the multiple RAMs. If a defective RAM is detected,...
6247154 Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self test  
This invention relates to a method and apparatus for combined stuck-fault testing and partial scan delay-fault built-in self testing (BIST). For partial scan delay-fault BIST, the circuit is...
6243307 Semiconductor device including tester circuit suppressible of circuit scale increase and testing device of semiconductor device  
After writing data into a memory cell array according to an internal address signal, data read out from each memory cell is compared with expected value data in a read out operation. When there are...
6239607 Simulation-based method for estimating leakage currents in defect-free integrated circuits  
A method for operating a data processing system to provide an estimate of the leakage current expected from an integrated circuit having a known test vector applied thereto. The method generates a...
6239603 Monitor TEG test circuit  
Monitor TEGs (Test Element Groups) for extracting the effects of process variations within a semiconductor chip and a test circuit therefor are provided to allow the monitor TEGs to be tested after...
6237123 Built-in self-test controlled by a token network and method  
This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order...
6237120 Program patching of a ROM  
A micro-controller integrated on a single substrate and which includes a read-only information memory for storing firmware, an address controller for performing address control, and an input port...
6228279 High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials  
By providing a photoresist material with a protective polymer layer during the etching of an organic anti-reflective coating, undue damage to the photoresist material can be avoided during opening...
6226779 Programmable IC with gate array core and boundary scan capability  
A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In...
6226753 Single chip integrated circuit with external bus interface  
A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit...
6219813 Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip  
A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two...
6219305 Method and system for measuring signal propagation delays using ring oscillators  
A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together...
6216254 Integrated circuit design using a frequency synthesizer that automatically ensures testability  
A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow...
6216243 Permanent failure monitoring in complex systems  
Described is a system with a plurality of subsystems, wherein at least one of the plurality of subsystems comprises one or more monitoring points relevant and representative for certain parameters...
6199122 Computer system, external storage, converter system, and recording medium for converting a serial command and data standard to a parallel one  
In order to access a memory card of the ATA specification, a computer generates a command based on the USB. A conversion controller in a reader/writer receives the command and converts it into a...
6189121 Semiconductor device containing a self-test circuit  
A semiconductor device having a self-test circuit which has an input signal generating circuit for generating a test signal in synchronization with a prescribed clock signal, a selector circuit for...
6185707 IC test software system for mapping logical functional test data of logic integrated circuits to physical representation  
The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of...
6185709 Device for indicating the fixability of a logic circuit  
A device for testing the fixability of logic circuits having an embedded memory. The logic circuit includes a built-in test circuit for generating data which tests the embedded memory. An...
6181614 Dynamic repair of redundant memory array  
A circuit arrangement and method of dynamically repairing a redundant memory array utilize dynamically-determined repair information, generated from a memory test performed on the redundant memory...
6182257 BIST memory test system  
A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and...
6175936 Apparatus for detecting faults in multiple computer memories  
Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory...
6163865 Built-in self-test circuit for read channel device  
A BIST circuit for use with a read channel device is disclosed that utilizes internally generated clock and control signals to control a test sequence. A linear feedback shift register is used as...
6163862 On-chip test circuit for evaluating an on-chip signal using an external test signal  
An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal...
6158033 Multiple input signature testing & diagnosis for embedded blocks in integrated circuits  
An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module...
6158028 Semiconductor integrated circuit  
At a test of built-in memory of a conventional semiconductor integrated circuit, data is written into the memory one address by one address and confirmed the data one by one, in case of mass memory...
6158031 Automated code generating translator for testing telecommunication system devices and method  
A system for testing a communication network component connected to a computer controlled apparatus via a data link in which the system automatically simulates telephonic communication with the...
6151692 Integrated circuit having memory built-in self test (BIST) for different memory sizes and method of operation  
An application-specific integrated circuit (ASIC) with a CPU module and a memory module connected to the CPU. The memory has a size selected from a set of alternative memory sizes. The CPU has a...
6148425 Bist architecture for detecting path-delay faults in a sequential circuit  
A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion...
6148426 Apparatus and method for generating addresses in a SRAM built-in self test circuit using a single-direction counter  
A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses...
6145104 Data processing system external pin connectivity to complex functions  
An integrated circuit containing a data processing system with a number of external peripheral pins utilizes the peripheral pins for both testing the corresponding peripherals and for parallel...
6145097 Method and apparatus for providing operand feed forward support in a data processing system  
The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for providing operand feed forward support in a data processing system...
6134505 Testing analog circuits using sigma-delta modulators  
An integrated circuit device has an analog block connected to a sigma-delta modulator. Analog signals from internal nodes in the analog block are fed to the sigma-delta modulator. The sigma-delta...
6131275 Methods and devices relating to circuit board constructions  
The present invention relates to a method for the parallel production of circuitry and software for a customised integrated circuit, primarily an ASIC-type circuit, mounted on a printed board...
6134685 Package parallel test method and apparatus  
A method for partial parallel testing a plurality of integrated circuit packages using a multi-package tester head having a plurality of sockets. Each socket is used for testing an integrated...
6134191 Oscillator for measuring on-chip delays  
A circuit separately measures one or both of the rising-edge and falling-edge signal propagation delays through a signal path of interest. The greater of these delays can then be used to establish...
6131174 System and method for testing of embedded processor  
An interlocutor system and method is described that allows for at-speed testing of an embedded microcontroller at the control of an embedded digital signal processor in a system-on-a-chip...
6125465 Isolation/removal of faults during LBIST testing  
A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches...
6119254 Hardware tracing/logging for highly integrated embedded controller device  
A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the...
6115789 Method and system for determining which memory locations have been accessed in a self timed cache architecture  
The present invention provides a method and system for providing observability of memory address access for self-timed cache designs. A system according to the present invention for determining...
6115763 Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit  
A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated...
6107814 Methods and circuits for testing open collectors and open drains  
The present invention is directed to methods and circuits for testing open collector or open drain output pads. In a preferred embodiment, the open collector or open drain outputs are hard driven...
6108798 Self programmed built in self test  
A memory (e.g. , Dynamic Random Access Memory (DRAM)) with self-programmable Built In Self Test (BIST). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM,...
6105154 Multi-bus multi-data transfer protocols controlled by a bus arbiter coupled to a CRC signature compactor  
A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having...
6101623 Current reduction circuit for testing purpose  
A detecting and testing circuit for detecting a leakage of current from LSI circuits mainly constituted by CMOS devices. The semiconductor integrated circuit includes a first circuit block having...
6085346 Method and apparatus for built-in self test of integrated circuits  
A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST routines are minimized, while also...
6071314 Programmable I/O cell with dual boundary scan  
A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In...
6070252 Method and apparatus for interactive built-in-self-testing with user-programmable test patterns  
Methods and apparatus for interactive built-in self-testing with user-programmable test patterns are disclosed. The present invention operates in the context of an integrated circuit (IC) including...
6070256 Method and apparatus for self-testing multi-port RAMs  
A method for and apparatus of testing a multi-port RAM (random access memory) detect single port faults and inter port shorts in multi-port random access memories. The algorithm performs a...
Matches 651 - 700 out of 1014 < 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 >