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6819609 |
Semiconductor memory device with built-in self-diagnostic function and semiconductor device having the semiconductor memory device
A semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to change and addition of test specifications without having to perform complicated control...
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6816991 |
Built-in self-testing for double data rate input/output
Macro cells for a Double Data Rate (DDR) I/O interface are provided. The macro cells feature built-in self-test (BIST) functionality for testing the I/O interface at speed, without using external...
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6816983 |
Microprocessor internally provided with test circuit
A microprocessor includes: a memory storing a program and various data; a processor core executing the program stored in the memory; an external bus interface serving as an interface portion of an...
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6813598 |
Logic simulation method and logic simulation apparatus
An MWL signal encoding part encodes a signal occurring on a main word signal line, an SD signal encoding part encodes a signal occurring on a subdecode signal line, a WL calculating part calculates...
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6813739 |
Scan interface chip (SIC) system and method for scan testing electronic systems
A can test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. In one embodiment, the present invention utilizes a scan test...
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6807645 |
Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failures
A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics. First multiplexers are respectively coupled between adjacent sequential channels of a plurality of...
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6802046 |
Time domain measurement systems and methods
Systems for performing time domain measurements of a device under test (DUT) are provided. One such system includes a normalization system that receives information corresponding to a model of a...
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6800817 |
Semiconductor component for connection to a test system
The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor component at a connection provided...
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6799289 |
On-board testing circuit and method for improving testing of integrated circuits
A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has...
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6799130 |
Inspection method and its apparatus, inspection system
The present invention relates to a tool for analyzing by priority a defect having a high possibility of causing an electrical failure when inspecting a particle and a pattern defect in a piece of...
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6795945 |
Method and arrangement for testing digital circuits
A method and an arrangement for testing digital circuits having at least one circuit logic and memory elements, which are interconnected to form at least one shift chain, in which test vectors are...
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6795942 |
Built-in redundancy analysis for memories with row and column repair
A method is presented for built-in redundancy analysis of a semiconductor memory device. The method does not require retention of an entire memory bitmap, and may be implemented on-chip and...
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6792560 |
Reliable hardware support for the use of formal languages in high assurance systems
A dataflow processor comprising a combiner for combining instructions and data, processing elements for carrying out the instructions, has error checking at the inputs to the processing elements...
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6789220 |
Method and apparatus for vector processing
A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift...
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6789221 |
Integrated circuit with self-test circuit
In an integrated circuit comprising an application circuit ( 1 ) to be tested and a self-test circuit ( 5 - 16 ) which is provided for testing the application circuit ( 1 ) and comprises an...
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6785857 |
Fixed-logic signal generated in an integrated circuit for testing a function macro integrated in an integrated circuit
A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro (1) for receiving signals whose...
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6784686 |
Semiconductor testing device
When a test pattern is output that shows that a program has shifted to a subroutine, a subroutine stay time measuring circuit starts counting a count value that shows a program stay time in the...
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6785837 |
Fault tolerant memory system utilizing memory arrays with hard error detection
A fault tolerant memory system and method of operation thereof. The fault tolerant memory system includes a number of memory arrays including at least one spare memory array, wherein each of the...
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6785846 |
Inexpensive method for diagnosing manufacturing defects in an embedded system
A system and method is provided for detecting defects in an embedded architecture or micro-processor based system. A look-up table, located with in a programmable logic device, is accessed to...
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6782498 |
Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification
In the semiconductor memory device, a control circuit generates various commands for a memory cell array according to an internal command control signal and an internal address signal output from...
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6782336 |
Test outputs using an idle bus
A test circuit receives a plurality of internal test signals and delivers a group of the plurality of internal test signals onto a bus during an idle state of the bus. The bus is coupled to output...
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6779145 |
System and method for communicating with an integrated circuit
A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an...
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6775798 |
Fast sampling test bench
An apparatus and method for using the apparatus for reducing analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing the...
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6775811 |
Chip design method for designing integrated circuit chips with embedded memories
A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in...
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6769080 |
Scan circuit low power adapter with counter
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
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6769081 |
Reconfigurable built-in self-test engine for testing a reconfigurable memory
A reconfigurable built-in self-test (“BIST”) engine for testing a reconfigurable memory is disclosed. The BIST engine executes a test on a memory for detecting faults. If the memory under test...
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6766486 |
Joint test action group (JTAG) tester, such as to test integrated circuits in parallel
A JTAG tester includes a JTAG controller in a PCI slot of a PC, a port multiplexer, a programmable power supply, and drive and compare logic, which tracks V cc . The tester reads and blows...
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6766488 |
Compressing information using CAM for narrow bit pattern output
A data compression device that serves the purpose of receiving large numbers of bits from inside a microcontroller or device under test which are fed to the data compression device featuring a...
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6762617 |
Semiconductor device having test mode entry circuit
A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the...
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6762614 |
Systems and methods for facilitating driver strength testing of integrated circuits
Integrated circuits (ICs) are provided. A representative IC includes a first pad that incorporates a first driver and a first receiver, with the first driver being configured to provide a first pad...
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6760865 |
Multiple level built-in self-test controller and method therefor
An integrated circuit has a Built-In Self-Test (BIST) controller ( 10 ) that has a sequencer ( 16 ) that provides test algorithm information for multiple memories ( 44, 46, 48, 50 ). The sequencer...
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6754864 |
System and method to predetermine a bitmap of a self-tested embedded array
A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of...
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6751762 |
Systems and methods for testing a memory
Systems and methods for testing a memory array in an integrated circuit. The method provides a favorable tradeoff between test time and quality of test results, by compressing data in a time...
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6741946 |
Systems and methods for facilitating automated test equipment functionality within integrated circuits
A preferred system for facilitating automated test equipment functionality within integrated circuits includes automated test equipment (ATE) configured to electrically interconnect with an...
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6738921 |
Clock controller for AC self-test timing analysis of logic system
A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data...
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6735731 |
Architecture for built-in self-test of parallel optical transceivers
Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test...
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6735746 |
Method and apparatus for TLB entry tracking, collision detection, and address reassignment, in processor testcases
A method of converting a testcase designed to execute on a first member of a processor family to a converted testcase for execution on a second member of a processor family provides particularly...
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6728916 |
Hierarchical built-in self-test for system-on-chip design
Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete...
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6728902 |
Integrated circuit having a self-test device for carrying out a self-test of the integrated circuit
An integrated circuit includes a self-test device which is provided for executing a self-test of the integrated circuit and which has a control output. A program memory is connected to the...
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6725407 |
Method and configuration for protecting data during a self-test of a microcontroller
The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of...
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6721912 |
Data carrier module having indication means for indicating the result of a test operation
A module ( 2 ) for a data carrier ( 1 ) includes an integrated circuit device ( 9 ) and transmission means ( 10 ), and the module ( 2 ) can be tested with the aid of test means ( 19 ) during a test...
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6718496 |
Self-repairing semiconductor device having a testing unit for testing under various operating conditions
A semiconductor device is provided having an internal circuit to be tested, a redundancy circuit used when detecting a defective part in the internal circuit, and a switching unit connected to the...
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6715118 |
Configuration for generating signal impulses of defined lengths in a module with a bist-function
In the configuration, the module can “learn” one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals,...
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6715105 |
Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port
A test method and apparatus allows simultaneous loading of multiple scan chains via a single common scan-in port (SDI) and a scan clock signal SCAN CLOCK. Data is scanned into one or more scanpaths...
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6711706 |
Method and apparatus for elastic shorts testing, a hardware-assisted wire test mechanism
A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive...
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6708317 |
Validating integrated circuits
A microprocessor core 4 is modeled using an obscured model 22 of the core functionality and a non-obscured model 24 of the scan chains that in that particular instance are associated with the...
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6704896 |
Method of and device for getting internal bus information
An internal bus information getting method can get information output onto an internal bus to facilitate detection of a malfunction position in a storage element stored in a microcomputer during...
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6701474 |
System and method for testing integrated circuits
A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at...
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6697979 |
Method of repairing integrated circuits
An arrangement and a method are provided for replacing defective units, which can be any desired unit of a chip (e.g., arithmetic and logic units), with a function unit. The arrangement and the...
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6697753 |
Methods and apparatus for testing electronic devices
Apparatus for testing an electronic device under a plurality of test conditions created during a test sequence includes an arbitrary waveform generator that sequentially generates the plurality of...
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