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7617425 Method for at-speed testing of memory interface using scan  
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
7613974 Fault detection method and apparatus  
This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a...
7596736 Iterative process for identifying systematics in data  
An iterative process for identifying systematics in data is provided. In general, a set of data is processed based on a signature definition to create a set of signature data. The set of signature...
7596733 Dynamically reconfigurable shared scan-in test architecture  
A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per...
7590904 Systems and methods for detecting a failure event in a field programmable gate array  
An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA...
7584386 Microprocessor comprising error detection means protected against an attack by error injection  
A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. In one...
7577888 Self learning signatures  
A system and method for monitoring processes corresponding to measurable values based on signatures associated with the measurable values is provided. The signatures can be created based on data...
7574644 Functional pattern logic diagnostic method  
A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the...
7568139 Process for identifying the location of a break in a scan chain in real time  
A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature...
7558994 Methods and apparatus for data compression  
A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including...
7539906 System for integrated data integrity verification and method thereof  
In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first...
7536619 RAM testing apparatus and method  
Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be...
7536615 Logic analyzer systems and methods for programmable logic devices  
A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for...
7533320 Wireless transmit/receive unit having a turbo decoder with circular redundancy code signature comparison and method  
An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The...
7533313 Method and apparatus for identifying outlier data  
A method for converting data includes generating a first data vector of data measurements related to processing of at least one workpiece. Each element of the first data vector is associated with...
7519889 System and method to reduce LBIST manufacturing test time of integrated circuits  
A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array...
7519878 Obtaining test data for a device  
Obtaining test data for a device under test includes obtaining a first part of the test data by testing the device at first points of a range of parameters using progressive sampling, and obtaining...
7516381 Integrated circuit test system  
A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor...
7509551 Direct logic diagnostics with signature-based fault dictionaries  
Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method...
7509550 Fault diagnosis of compressed test responses  
Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error...
7509548 Method and apparatus for integrated circuit self-description  
An integrated circuit includes a self-description data store that stores a self-description of at least a portion of the integrated circuit device. The self-description includes at least some...
7506234 Signature circuit, semiconductor device having the same and method of reading signature information  
A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature...
7506217 Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability  
A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update...
7500164 Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies  
A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not...
7500163 Method and apparatus for selectively compacting test responses  
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor...
7500162 Sourcing internal signals to output pins of an integrated circuit through sequential multiplexing  
An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input...
7500148 Test apparatus and testing method  
There is provided a testing apparatus that tests a device under test. The testing apparatus includes: a command executing unit operable to sequentially execute commands included in a test program...
7493542 Arrangement for testing integrated circuits  
The invention relates to an arrangement for testing integrated circuits, to a test system ( 2 ), to a circuit ( 1 ) to be tested, and to a method of testing logic circuits, where the test system (...
7487420 System and method for performing logic failure diagnosis using multiple input signature register output streams  
A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a...
7487419 Reduced-pin-count-testing architectures for applying test patterns  
Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed...
7486205 Compression and decompression of stimulus and response waveforms in automated test systems  
An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus...
7484148 Interface error monitor system and method  
An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with...
7480882 Measuring and predicting VLSI chip reliability and failure  
This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These...
7478304 Apparatus for accelerating through-the-pins LBIST simulation  
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device  
A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not...
7475311 Systems and methods for diagnosing rate dependent errors using LBIST  
Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target...
7474999 Method for accounting for process variation in the design of integrated circuits  
A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components...
7461312 Digital signature generation for hardware functional test  
A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period...
7461311 Device and method for creating a signature  
A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words...
7461309 Systems and methods for providing output data in an LBIST system having a limited number of output ports  
Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry...
7451372 Circuit test pattern edition apparatus, circuit test pattern editing method, and signal-bearing medium embodying a program of circuit test pattern edition  
An apparatus that edits a test pattern used in a circuit function test includes a generator that generates a regular pattern that includes a plurality of unit patterns, by inserting a redundant...
7441165 Read-only memory and operational control method thereof  
A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a...
7437642 Model train command protocol using front and back error bytes  
A model train command protocol using front and back error bytes is disclosed. The front error byte is used to encode the data so that it is securely transmitted. The back error byte checks for...
7437641 Systems and methods for signature circuits  
Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under...
7437638 Boundary-Scan methods and apparatus  
Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to...
7434152 Multiple-level data compression read mode for memory testing  
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one...
7412638 Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit  
A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes...
7409614 Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit  
A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the...
7404126 Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs  
Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning...
7404115 Self-synchronising bit error analyser and circuit  
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus...
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