Matches 101 - 150 out of 303 < 1 2 3 4 5 6 7 >
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6834364 Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences  
A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before...
6831647 Raster engine with bounded video signature analyzer  
An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a...
6819327 Signature analysis registers for testing a computer graphics system  
A signature capture and analysis system suitable for use in a high performance computer graphics system is described. The system employs a distributed network of signature analysis registers (SARs)...
6807645 Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failures  
A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics. First multiplexers are respectively coupled between adjacent sequential channels of a plurality of...
6807504 Apparatus for testing I/O ports of a computer motherboard  
An apparatus for testing I/O ports of a computer motherboard. A non-volatile memory on a computer motherboard under test stores a test code instead of a normal BIOS code to initialize the computer...
6789220 Method and apparatus for vector processing  
A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift...
6789219 Arrangement and method of testing an integrated circuit  
In an arrangement for testing an integrated circuit comprising at least two circuit sections ( 1, 2 ) which in normal operation operate with at least two different clock signals, a minimal number...
6754864 System and method to predetermine a bitmap of a self-tested embedded array  
A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of...
6751765 Method and system for determining repeatable yield detractors of integrated circuits  
An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test...
6745370 Method for selecting an optimal level of redundancy in the design of memories  
A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect...
6738921 Clock controller for AC self-test timing analysis of logic system  
A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data...
6725407 Method and configuration for protecting data during a self-test of a microcontroller  
The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of...
6715105 Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port  
A test method and apparatus allows simultaneous loading of multiple scan chains via a single common scan-in port (SDI) and a scan clock signal SCAN CLOCK. Data is scanned into one or more scanpaths...
6701477 Method for identifying the cause of yield loss in integrated circuit manufacture  
A method for determining the integrated circuit manufacturing operations that are the principle contributors to defect limited test yield loss comprises extracting the electrical faults for the...
6684357 Chip testing apparatus and method  
A chip testing apparatus and method including a testing section, provided in a corresponding chip, for judging a normal/abnormal state of the corresponding chip by obtaining a test signature by...
6681357 MISR simulation tool for memory BIST application  
A method and tool for simulating a multiple input signature register for a memory test application is provided. Further, a method and tool for signature simulation based on a configuration, type,...
6658616 Method for improving the efficiency of weighted random pattern tests through reverse weight simulation using effective pattern masks  
A method is defined which reduces the number of applied test patterns while maintaining identical fault coverage for a given set of weighted random patterns. Reduction is accomplished by simulating...
6647526 Modular/re-configurable test platform  
A system and method is provided for testing industrial control modules. Input and output stimulus signals, communication lines, measurement device lines and relay contacts are provided at a tester...
6629278 Compressed data restoration apparatus, semiconductor tester equipped with same, and data compression/restoration method  
A compressed data restoration apparatus comprises a first storage unit 10 for storing therein a main file 20 composed of a plurality of unit files 24 each including a compressed data row 28 ...
6629279 Method and system for testing the performance of DSP  
A method of testing the performance of real time DSP algorithms after customer code has been added and includes the steps of embedding a signature equation in the DSP code that calculates to a...
6625688 Method and circuit for analysis of the operation of a microcontroller using signature analysis of memory  
A method and circuit for determining the health of a microcontroller is provided having a circuit that includes a bus, a CPU coupled to the bus and a register coupled to the bus. A memory is also...
6600686 Apparatus for recognizing chip identification and semiconductor device comprising the apparatus  
A semiconductor device having an apparatus is provided for recognizing chip identification capable of minimizing the number of pads. The apparatus for recognizing chip identification comprises a...
6571363 Single event upset tolerant microprocessor architecture  
A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two...
6567017 Configurable code generator system for spread spectrum applications  
A configurable code generator system (CGS) for spread spectrum applications is disclosed herein. The CGS includes a composite code generator unit (CGU), a global code generator, and an interface...
6564348 Method and apparatus for storing and using chipset built-in self-test signatures  
A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data...
6557132 Method and system for determining common failure modes for integrated circuits  
A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs...
6553530 Integrated circuit devices that include self-test apparatus for testing a plurality of functional blocks and methods of testing same  
Integrated circuit devices have a self-test capability in which a sequence of input data patterns are generated by a test pattern unit and are selectively applied to a functional or test block that...
6543019 Method for built-in self test of an electronic circuit  
The built-in self test method enables common and concurrent self testing of the combinatorial logic and the memory of an electronic circuit. The common self test circuit for the logic and the...
6539266 Computer system, method of executing computer program, and computer program storage medium  
A computer system for detecting alteration of programs in which a plurality of check program portions are read from a storage medium which carries computer programs including the check program...
6539508 Methods and circuits for testing programmable logic  
Described is a test circuit that can be instantiated on a programmable logic device to perform at-speed functional tests of programmable resources, including internal memory and routing resources....
6536007 Models and technique for automated fault isolation of open defects in logic  
A method and system for diagnosing open defects in logic circuits. The method employs a pair of diagnostic fault models and an associated algorithm to automate the diagnoses of open...
6529030 IC testing apparatus  
In a circuit 10 of an IC testing apparatus 1 in which a wave-form of a pattern signal 2 a outputted from a pattern generator 2 is shaped and timing of the pattern signal is adjusted so that...
6516432 AC scan diagnostic method  
Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and...
6457145 Fault detection in digital system  
For fault testing in a digital system, a processor unit is made available from other activities and the logical units to be tested are set to a predetermined state. An output response analyze is...
6449755 Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker  
A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access...
6442723 Logic built-in self test selective signature generation  
LBIST resource parameters are used to control the data inputs for the signature generation process. These resource parameters include a LBIST pattern cycle counter, a channel input selected to...
6438048 Nonvolatile memory and high speed memory test method  
A nonvolatile memory device has a signature code generator generating an new signature code as a function of data read from the cell array and the previously calculated signature code. Data are...
6374370 Method and system for flexible control of BIST registers based upon on-chip events  
A method and structure facilitates the debugging and test coverage capabilities of a microprocessor. A microprocessor having memory arrays, a debug block, and one or more built-in-self-test (BIST)...
6370658 Device for testing digital signal processor in digital video disc reproducing apparatus  
A device for testing a digital signal processor in a DVD (Digital Video Disc) reproducing apparatus. The test device includes a computer for generating test data for testing the digital signal...
6367029 File server system tolerant to software and hardware failures  
A file server system tolerant to hardware and software failures is located over a plurality of hardware nodes. The nodes of the system act as hosts for software components of the system. Several of...
6357026 System and method for at-speed interconnect tests  
A system and method for detecting speed related defects in an electronic assembly includes application specific integrated circuits (ASICs) designed with registered I/O's to provide true at-speed...
6327685 Logic built-in self test  
A BIST method that modifies the scan chain path and scan clocks to allow for distributed BIST test. In this distributed BIST concept, the Linear Feedback Shift Register (LFSR) and the Multiple...
6327677 Method and apparatus for monitoring a network environment  
A system is provided that monitors a network environment. The system collects recent data associated with operation of the network environment. The network environment is analyzed by comparing the...
6311311 Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test  
A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate...
6282134 Memory test method and nonvolatile memory with low error masking probability  
A nonvolatile memory device has a signature code generator generating a present signature code from an algorithm modified dynamically as a function of predefined varying parameters. A variable...
6240537 Signature compression circuit and method  
A parallel signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is...
6233361 Topography processor system  
A topography processor system comprising a phased image sensor array, at least one processor arranged to perform range decompression of imaged detail, and a means for allowing non interruptive...
6199184 Parallel signature compression circuit and method for designing the same  
A parallel signature compression circuit includes two or more MISRs (multiple input signature registers) coupled in series. The signature compression circuit allows the error effect of at least one...
6185712 Chip performance optimization with self programmed built in self test  
An integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon...
6172966 Diagnosis of networks of components, with stripwise modeling  
An n-tuple defines an envelope of a variable over a time interval. An input memory receives blocks of measurements made at known points of the network and converts them into initial n-tuples. In a...
Matches 101 - 150 out of 303 < 1 2 3 4 5 6 7 >