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7404126 Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs  
Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning...
7401280 Self-verification of configuration memory in programmable logic devices  
In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit...
7376875 Method of improving logical built-in self test (LBIST) AC fault isolations  
A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to...
7370254 Compressing test responses using a compactor  
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can...
7353430 Device for validating an integrated circuit  
A device ( 10 ) for validating a circuit ( 1 ) comprising at least one microprocessor ( 3 ) and a specialized unit ( 2 ) provided with registers includes a base ( 11 ) for receiving the circuit, a...
7353474 System and method for accessing signals of a user design in a programmable logic device  
Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler,...
7337375 Diagnostics of cable and link performance for a high-speed communication system  
A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error...
7325181 Method and device for selecting the operating mode of an integrated circuit  
A device for selecting an operating mode of an integrated circuit, including a non-volatile memory programmable after manufacturing exhibiting prior to any programming an initial content, means for...
7308630 Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit)  
Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled...
7302624 Adaptive fault diagnosis of compressed test responses  
Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures...
7302626 Test pattern compression with pattern-independent design-independent seed compression  
The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent...
7278048 Method, system and computer program product for improving system reliability  
A method and system for improving the reliability of a system, such as a software system, is disclosed. “Service measurements” that are routinely measured and monitored in connection with the...
7272767 Methods and apparatus for incorporating IDDQ testing into logic BIST  
Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG)...
7260757 System and method for testing electronic devices on a microchip  
A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple...
7254760 Methods and apparatus for providing scan patterns to an electronic device  
In one embodiment, a method provides scan patterns to an electronic device having BIST hardware. The BIST hardware has production and diagnostic test modes, and the device outputs one or more...
7251747 Method and system for transferring data using a volatile data transfer mechanism such as a pipe  
Methods and systems for efficient and accurate re-starting of data transfers using volatile data transfer mechanisms, such as pipes, following an error. According to one embodiment, portions of the...
7231621 Speed verification of an embedded processor in a programmable logic device  
Method and apparatus for generating a test program for a programmable logic device having an embedded processor. Predetermined code is obtained to exercise at least one speed limiting path...
7225373 Data transfer validation system  
System and apparatus for data validation is described. An initialization controller includes an initialization state machine. The initialization state machine is configured to cause configuration...
7210083 System and method for implementing postponed quasi-masking test output compression in integrated circuit  
The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test...
7203878 System and method for performing predictable signature analysis in the presence of multiple data streams  
A computer system may include several integrated circuits and a routing circuit configured to route several data streams between the integrated circuits. The routing circuit includes several input...
7203879 Built-in-test diagnostic and maintenance support system and process  
A diagnostic and maintenance support system and process are provided for performing tests, collecting Built-In-Test (BIT) log data from systems, analyzing fault data, and recommending Shop...
7185252 Measurement circuit and method for serially merging single-ended signals to analyze them  
Provided are a measurement circuit and method for serially merging single-ended signals to analyze them. To analyze two differential signals probed from a DUT, that is, DP and DM signals, the...
7178078 Testing apparatus and testing method for an integrated circuit, and integrated circuit  
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a...
7178068 Memory image verification system and method  
A system and method of verifying a dumped memory image following a crash of a computer system that includes physical memory, a system kernel, and a virtual memory system. At least a portion of the...
7155652 Digital signal processing for real time classification of failure bitmaps in integrated circuit technology development  
A system and method for processing tester information is provided having a system-under-test. A pattern is written to the system-under-test, and a pattern is read therefrom. The pattern written is...
7155648 Linear feedback shift register reseeding  
An apparatus has an integrated circuit that includes a seed register, a linear feedback shift register to load a test vector into a number of scan chains, and a signature register to receive a test...
7143324 System and method for automatic masking of compressed scan chains with unbalanced lengths  
A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e.,...
7139956 Semiconductor integrated circuit device and test method thereof  
A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal....
7139953 Integrated circuit with test circuit  
Integrated circuit with an application circuit ( 1 ) to be tested, and a self-test circuit ( 5 - 16 ) which is provided for testing the application circuit ( 1 ) and comprises an arrangement ( 5 -...
7137050 Compression circuit for testing a memory device  
An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input circuit is adapted to receive at least a...
7131046 System and method for testing circuitry using an externally generated signature  
A system and method that enables testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable...
7096397 Dft technique for avoiding contention/conflict in logic built-in self-test  
A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern...
7093174 Tester channel count reduction using observe logic and pattern generator  
Test logic supports the testing of an electronic circuit, where the number of ports of the electronic circuit exceeds the number of available tester IO channels. In some examples, the test logic...
7089514 Defect diagnosis for semiconductor integrated circuits  
A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are...
7058870 Method and apparatus for isolating faulty semiconductor devices in a multiple stream graphics system  
A method and an apparatus are provided for isolating faulty semiconductor devices in a multiple stream graphics system. The apparatus includes a buffer adapted to receive a plurality of data...
7047469 Method for automatically searching for and sorting failure signatures of wafers  
A method of searching for and sorting failure signatures of wafers is provided. First, a failure signature database is built up for recording a plurality of failure signature data, wherein each...
7039844 Integrated circuit with self-testing circuit  
An integrated circuit ( 14 ) with an application circuit ( 1 ) to be tested and a self-testing circuit ( 5 - 13 ), which is provided for testing the application circuit ( 1 ) and generates...
7003432 Method of and system for analyzing cells of a memory device  
A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages...
6978407 Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory  
A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for...
6971054 Method and system for determining repeatable yield detractors of integrated circuits  
An exemplary embodiment of the present invention is a method for testing an integrated circuit. The method includes generating a test pattern and generating a reference signature corresponding to...
6968478 Method and apparatus for data transfer validation  
Method and apparatus for data transfer validation is described. Configuration data is obtained. A signature for the configuration data is generated. The configuration data and the signature are...
6964004 Method and apparatus for testing a system-on-a-chip  
A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications...
6961886 Diagnostic method for structural scan chain designs  
A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains...
6920596 Method and apparatus for determining fault sources for device failures  
A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of...
6901543 Utilizing slow ASIC logic BIST to preserve timing integrity across timing domains  
A logic built-in self-test controller is disclosed. The invention, in its various aspects and embodiments, is a built-in self-test controller capable of performing a logic built-in self-test at a...
6883127 Comparison circuit and method for verification of scan data  
An apparatus and a method are disclosed to save on the integrated circuit die(s) the state of the scan latches coupled to an integrated circuit in a memory unit during an exercise of the integrated...
6880119 Method for supervising parallel processes  
The present invention relates to a method of supervising parallel processors in a data system that comprises a first system CP-A and a second system CP-B. The method comprises the steps of: ...
6873330 System and method for performing predictable signature analysis  
In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The data output by the first component...
6857092 Method and apparatus to facilitate self-testing of a system on a chip  
A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor....
6834368 Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit  
This invention provides a semiconductor integrated circuit in which test facilitation technology (design for testability) of system on a chip (SOC) constructed of functional blocks or intellectual...
Matches 51 - 100 out of 303 < 1 2 3 4 5 6 7 >