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7627795 Pipelined data processor with deterministic signature generation  
A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging...
7627066 Apparatus for data recovery in a synchronous chip-to-chip system  
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling...
7624322 Scan based testing of an integrated circuit containing circuit portions operable in different clock domains during functional mode  
An integrated circuit containing an encoder which avoids setup/hold violation in a memory element of one clock domain, when receiving data from another memory element of another clock domain during...
7624319 Performance monitoring system  
A system for validating data collected in a first clock domain. A performance counter is disposed in a second clock domain to perform performance computations relative to the data. Validation...
7623482 System and method for effectuating the transfer of data blocks including a header block across a clock boundary  
A system and method for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain. In one embodiment, a first...
7617431 Method and apparatus for analyzing delay defect  
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
7613972 Semiconductor integrated circuit, and designing method and testing method thereof  
A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational...
7613971 Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit  
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an...
7613969 Method and system for clock skew independent scan register chains  
A method and system for clock skew independent scan chains. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan...
7613967 Inversion of scan clock for scan cells  
A device includes a scan circuit including a scan chain. The scan chain includes a first plurality of scan cells that receive a first scan clock signal in a first clock domain. A second plurality...
7613599 Method and system for virtual prototyping  
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are...
7607061 Shrink test mode to identify Nth order speed paths  
In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock...
7600167 Flip-flop, shift register, and scan test circuit  
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
7596732 Digital storage element architecture comprising dual scan clocks and gated scan output  
A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave...
7590504 Graphical user interface for creation of IBIST tests  
A graphical user interface (GUI) that configures a test for a circuit. More particularly, the circuit includes a built-in-self-test (BIST) compatible device and has a test configuration. The device...
7574635 Circuit for and method of testing a memory device  
Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a...
7574633 Test apparatus, adjustment method and recording medium  
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable...
7571402 Scan chain modification for reduced leakage  
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
7571366 Sequential signals selecting mode and stopping transfers of interface adaptor  
A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises...
7562266 Method and device for verifying timing in a semiconductor integrated circuit  
A timing verification device for performing effective timing verification while correctly taking variation into account. The timing verification device receives a technology file and extracts a...
7558998 Semiconductor apparatus and clock generation unit  
A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input...
7558722 Debug method for mismatches occurring during the simulation of scan patterns  
A method and system are disclosed for testing for double shift errors in at least one scan chain of flip-flops during a simulation of the design of a digital integrated circuit chip. At the start...
7552372 Semiconductor device and test method thereof  
An LSI has bidirectional buffers connected to a boundary scan circuit. The boundary scan circuit 12 has asynchronous setting circuits for setting each bidirectional buffer to input mode or output...
7549101 Clock transferring apparatus, and testing apparatus  
There is provided a clock transferring apparatus for synchronizing a pattern signal synchronized with a reference clock with a variable clock based on an oscillation source different from that of...
7549092 Output controller with test unit  
There is provided an output controller with a test unit, which can test an appropriate delay amount according to an operating frequency under a real situation. The output controller includes an...
7548105 Method and apparatus for source synchronous testing  
A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be...
7546504 System and method for advanced logic built-in self test with selection of scan channels  
A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or...
7543210 Semiconductor device and test system thereof  
A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating...
7543205 Control signal synchronization of a scannable storage circuit  
A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a...
7539916 BIST to provide phase interpolator data and associated methods of operation  
In an embodiment, a phase interpolator (PI) circuit is in an integrated circuit with a test latch, and the test latch is enabled by a test clock signal to under-sample the PI output clock signal...
7538558 Failure detection apparatus and failure detection method for a semiconductor apparatus  
A failure detection apparatus for a semiconductor apparatus includes a clock line to transmit a clock signal, a shield line to shield the clock line, an inverted signal setting unit to supply...
7536618 Wide frequency range signal generator and method, and integrated circuit test system using same  
A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the...
7536617 Programmable in-situ delay fault test clock generator  
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in...
7529996 DDR input interface to IC test controller circuitry  
A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is...
7526697 Memory test circuit and method  
To test memories operating with different operational clocks and deal with a delay involved in testing a memory at a physically remote location. A memory test circuit of the present invention tests...
7519880 Burn-in using system-level test hardware  
A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a...
7516380 BIST to provide jitter data and associated methods of operation  
In an embodiment, a transmitter circuit is in an integrated circuit die with a test latch, and the test latch is enabled by a test clock signal to under-sample the transmit signal from the...
7516379 Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)  
A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), includes an IC logic element, a scan chain, and a calibration circuit including a first...
7516374 Testing circuit and related method of injecting a time jitter  
A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the...
7512856 Register circuit, scanning register circuit utilizing register circuits and scanning method thereof  
The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled...
7512855 Shift register circuit  
A shift register circuit which having a plurality of stages, a signal of the timing controller is conveyed to the shift register circuit for generating and transferring a sample signal to data...
7512854 Method and apparatus for testing, characterizing and monitoring a chip interface using a second data path  
A data receiver circuit in a receiving chip provides the capability to characterize an interface, which includes one or more inter-chip communication lines, between a transmitting chip and the...
7509545 Method and system for testing memory modules  
A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two...
7506233 Interface circuit and method of testing or debugging semiconductor device using it  
An interface circuit includes a selection circuit receiving first and second signals, generating a time division serial signal by selecting one of the first and second signals in response to the...
7506230 Transient noise detection scheme and apparatus  
A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches....
7500165 Systems and methods for controlling clock signals during scan testing integrated circuits  
The present invention is directed to systems and method of controlling clock signals during scan testing integrated circuits. The methods and systems provide efficient at-speed scan testing while...
7500034 Multiple integrated circuit control  
In an implementation of multiple integrated circuit control, a multiple integrated circuit controller initiates and controls data transactions between the multiple integrated circuit controller and...
7496813 Communicating simultaneously a functional signal and a diagnostic signal for an integrated circuit using a shared pin  
An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared...
7496803 Method and apparatus for testing an integrated device's input/output (I/O)  
A plurality of timing diagrams and different versions of circuits to test an integrated device in a test mode of operation. The invention allows for pulling in a strobe and eliminating the need for...
7492793 Method for controlling asynchronous clock domains to perform synchronous operations  
A method for controlling asynchronous clock domains to perform synchronous operations is provided. With the method, when a synchronous operation is to be performed on a chip, the latches of the...
Matches 1 - 50 out of 398 1 2 3 4 5 6 7 8 >