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8984358 IC TAP with address, state monitor, and state decode circuitry  
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for...
8904249 At speed testing of high performance memories with a multi-port BIS engine  
A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality...
8839057 Integrated circuit and method for testing memory on the integrated circuit  
An integrated circuit includes memory units and at least one memory test module, each module includes one associated memory unit, a set of test registers therefor, and a test engine configured to...
8707114 Semiconductor device including a test circuit that generates test signals to be used for adjustment on operation of an internal circuit  
A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code...
8677306 Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC  
A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric...
8595584 Method and apparatus for interleaving a data stream using quadrature permutation polynomial functions (QPP)  
A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation...
8543966 Test path selection and test program generation for performance testing integrated circuit chips  
A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated...
8504887 Low power LDPC decoding under defects/erasures/puncturing  
This disclosure relates generally to low power data decoding, and more particularly to low power data decoders for use under defects, erasures, and puncturing, with a low density parity check...
8495443 Secure register scan bypass  
An apparatus and method for protecting the contents of a secure register from scan accessibility is disclosed. The secure register may include a number of scannable elements within a scan chain....
8433963 Address and command port connecting trace circuitry and TAP domain  
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and...
8375275 Electronic storage device and control method thereof  
An electronic storage device for connecting with a host system includes a flash memory including a number of memory segments, and a controller including an error correction segment capable of...
8166358 Test access port with address and command capability  
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for...
8136002 Communication between controller and addressed target devices over data signal  
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin....
8055964 Semiconductor device having plural clock domains which receive scan clock in common  
A semiconductor device, includes a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan...
8010856 Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains  
In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the...
7965568 Semiconductor integrated circuit device and method of testing same  
A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip...
7908530 Memory module and on-line build-in self-test method thereof for enhancing memory system reliability  
A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit...
7821226 Method for the allocation of addresses in the memory cells of a rechargeable energy accumulator  
A method for placing addresses in the memory cells of a rechargeable energy storage device for use in a motor vehicle, each of which memory cells includes at least one sensor device and an...
7801254 Address generator for LDPC encoder and decoder and method thereof  
An address generator for providing an address to one of a linear block encoder and a soft linear block code decoder comprises a counter to count c, a position of a bit within a codeword of user...
7770084 Selectable JTAG or trace access with data store and output  
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin....
7757145 Test method, integrated circuit and test system  
The test method, integrated circuit and test system embodiments disclosed herein relate to testing at least one integrated circuit which uses an internal operating clock and has a first number of...
7716550 Semiconductor IC including pad for wafer test and method of testing wafer including semiconductor IC  
Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address...
7640124 Delay failure test circuit  
In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test...
7617425 Method for at-speed testing of memory interface using scan  
A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory...
7571402 Scan chain modification for reduced leakage  
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
7571364 Selectable JTAG or trace access with data store and output  
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin....
7539913 Systems and methods for chip testing  
Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage...
7506210 Method of debugging PLD configuration using boundary scan  
Methods and tools for detecting and correcting problems arising in the configuration process of a programmable logic device are described. An analyzer is used to aid a user in debugging the...
7484152 Securing the test mode of an integrated circuit  
An electronic circuit includes a logic circuit formed from a plurality of logic units. The electronic circuit also includes a plurality of memory units capable of forming a shift register, capable...
7475313 Unique pBIST features for advanced memory testing  
This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used...
7454673 Apparatus, system, and method for accessing persistent files in non-execute-in-place flash memory  
Persistent files stored in non-XIP flash memory are accessed during operation of an electronic device. During execution of application code on the device, the persistent files are accessed using...
7447956 Method and apparatus for testing data steering logic for data storage having independently addressable subunits  
Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected...
7444573 VLCT programmation/read protocol  
An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit...
7444577 Memory device testing to support address-differentiated refresh rates  
A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from...
7437643 Automated BIST execution scheme for a link  
Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training...
7418636 Addressing error and address detection systems and methods  
Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is...
7403901 Error and load summary reporting in a health care solution environment  
A system, method and computer program are provided for generating error and summary reports for a data load. A plurality of records to be loaded in a database are received. The records may include...
7383480 Scanning latches using selecting array  
A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at...
7281179 Memory device and input signal control method of a memory device  
A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is...
7231563 Method and apparatus for high speed testing of latch based random access memory  
A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock...
7206237 Apparatus and method for testing a memory device with multiple address generators  
An apparatus includes a test signal path to provide a test signal to a memory cell array responsive to an address generating command, the test signal to access a memory cell within the memory cell...
7032141 Semiconductor device including test-facilitating circuit using built-in self test circuit  
A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three...
6963963 Multiprocessor system having a shared main memory accessible by all processor units  
A data processing (10) includes memory management circuitry (14) which allows additional control over the physical address (83) and over the address attributes (84) which are provided for use by...
6836440 Method of checking electrical connections between a memory module and a semiconductor memory chip  
Two methods check functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor...
6769084 Built-in self test circuit employing a linear feedback shift register  
A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test...
6728915 IC with shared scan cells selectively connected in scan path  
This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in control scan cells are dedicated...
6717235 Semiconductor integrated circuit device having a test path  
The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with...
6711708 Boundary-scan test method and device  
There is provided a boundary-scan test device incorporated into a semiconductor integrated circuit for running self-diagnostics on the semiconductor integrated circuit. The device comprises a...
6694461 System and method for testing integrated memories  
An address generator provides for generation of addresses for a plurality of different tests by allowing for primitive polynomial-based pseudo-random bit-streams to be shifted into the address...
6678850 Distributed interface for parallel testing of multiple devices using a single tester channel  
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester...

Matches 1 - 50 out of 99 1 2 >